Optimization And Implementation Of Intra Frame Of AVS Encoder On On-chip Cloud Architecture

With the development and progress of information technology, digital video communication has also become one of the hot topics in the research. AVS standard is the digital video and audio coding standard possessing independent intellectual property rights and established by Audio and Video Coding Standard Workgroup of China, whose performance is neck and neck with H.264standard. AVS standard has become the basic standard in such important audio and video applications as high definition television, internet television, video communication and so forth in China.A series of advanced technologies are applied in AVS standard to improve the video coding efficiency and the data throughput of real-time encoding. FPGA has rich register and logic resources, its high performance and flexibility can satisfy the need of high speed and complicated electronic circuit design.In this subject, a new architecture is proposed-On-chip cloud architecture, the optimization and implementation of intra frame of AVS encoder is completed on this architecture. On-chip write-only bus (BoW) and message access mechanism based on BoW are designed. The network topology structure of BoW is simple for highly parallel and pipeline processing of atom components, suitable for processing video encoding algorithms of big data and high complexity. AVS algorithm module is packaged into atom component accessed based on messages, which are connected to bus through uniform node interface.According to the characteristic of AVS coding, intra frame of AVS encoder is implemented on FPGA in this paper. There are five functional modules in the implementation of intra frame of AVS encoder, which are packaged into atom components accessed based on messages, including image capture atom component, luminance prediction and transform atom component, luminance encoding atom component, chroma prediction and transform atom component, chroma encoding atom component. Considering the features of intra frame and granularity division principles of atom component synthetically, the traditional data block mode of using16×16macroblock as the basic unit is replaced and thinned into the mode of8×8block. The smaller granularity division method reduces the connection time between atom component and process engine, well saving hardware resources and improving coding efficiency.To improve the speed of data processing and realize real-time video encoding, each module utilizes the method of highly parallel algorithm and pipeline technique. Taking the advantage of the architecture, the efficiency of encoding is improved further by deploying multiple atom components repeatedly and calling multiple processes in parallel, which achieves the real-time encoding of high resolution images. Synthesized by ISE and simulated by ModelSim, the maximum clock frequency can be up to130MHz, implementing the real-time encoding of D1resolution intra frame images on Virtex-5platform.