Research On U-SoC On-chip Cloud Architecture For Video Coding Application

Since the invention of the first integrated circuit, the characteristics of semiconductor products have been developing alternatively along "Special" and "General" with the fluctuation cycle of a decade. Currently semiconductor products are in the special-purpose stage distinguished by SoC. Yet with the increase of single-chip integration density, the SoC system characterized by bus can hardly solve the problems of limited address space and power consumption caused by single clock synchronization. Chinese scholar and academician Xu Juyan predicted that the user-reconfigurable system on chip (U-SoC) which is universal in a particular domain will be the feature of the next generation of general-purpose semiconductor products. U-SoC, as the raw chip, achieves designated application functions through users’reconstructing hardware by software programming. Reconfigurable SoC has become the hotspot of academic research at home and abroad, and to carry out the research of reconfigurable system is of great significance for accelerating the development of China’s microelectronics industry.Cloud computing parallel processing and resource virtualization features are introduced to the U-SoC architecture design in this paper, and the three-layer SOA on-chip cloud architecture, "require+semantic+serve", is proposed. The concept of component in software field is atomized and implemented into coarse-grained instruction set; the basic functional modules in the circuit are encapsulated into atom components connected by messages, and the basic framework of on-chip cloud is built through the atom components interconnected by on-chip write-only bus. Research is done on problem-resolving model, application layer language LL7 (Language Level 7) and on-chip bus interconnect mechanism of the raw chip under on-chip cloud architecture. Problem-resolving model includes modeling platform and process design platform, which is the application development environment of raw chip; define the application layer language LL7, including domain instruction set (LL7-PS) and application process engine (LL7-PI), and describe application scenarios into semantic processes and load them to the engine for execution; on-chip cloud architecture is implemented through on-chip write-only bus and its interconnection mechanism, including resource relevent access protocol (application layer), uniform component access protocol (network layer) and uniform node interface access protocol (link layer). LL7 and on-chip cloud architecture are achieved with component-based IP cores and deployed inside chips to increase instruction granularity and improve parallelism. This makes raw chip programmable and reconfigurable to users in two dimensions, syntax elements and semantic process, realizing a design approach of directly generating IC chips from the algorithms.In order to establish the environment for AVS coding application, a Real-time video process system is designed in this paper, which can receive standard or non-standard video input signals, and it possesses the functions of AVS encoding, auto-focus, deinterlacing, format conversion, frame rate enhance, image enlarge, image filtering and so on. An improved gray difference auto-focusing algorithm is proposed, and mountain-climb searching strategy is adopted and focus motor driven to obtain maximum focus evaluation function value of the current image, achieving auto-focusing. Inter-field difference algorithm is used to implement de-interlacing. A dual-port DDR2 SDRAM controller is designed to meet the synchronous access to DDR2 memory of two ports, improving efficiency, and this controller is applied to improve frame rate, the maximum frame rate being up to 75Hz. The specific scale factor image magnification algorithm is adopted to achieve real-time video image amplification, and the output resolution can be enlarged to 1280×768. Segmental linear transformation is used to enhance image contrast. Median filtering algorithm is adopted to achieve real-time video image filtering. The modules of video processor are all described with VHDL and verified on Xilinx FPGA development platform.The AVS video coding standard is implemented and veried with the traditional designing method. Using the parallel processing capabilities of FPGA and adopting VHDL hardware description language, the hardware implementation of such modules as intra prediction, inter prediction, residuals, integer DCT, quantization, entropy coding, inverse quantization, IDCT inverse transform, reconstruction, loop filter and so on is completed. And the D1 resolution AVS encoder, with the working mode of state machine, is achieved on Xilinx XUP V5-LX110T FPGA platform. Finally, the above moduls are packaged into atom components with message connection.With the atom component set for AVS coding algorithm, we design an universal U-SoC raw chip in a particular domain. Using U-SoC on-chip cloud architecture and the integrated circuit design method based on this architecture, an autonomous AVS encoder is designed. Analyzing the functions of AVS encoder, the three-layer SOA model is built, and system use cases, system scenarios and atom component set are obtained through requirement layer analysis. The application layer language AVS-LL7 of AVS encoder is defined in semantic layer to get the semantic process set of AVS encoder. Service layer achieves AVS atom component set and defines component data frame format. The semantic process described with avsLL7 is loaded into the sequencer engine process queue, automatically deployed by the engine and calling atom component, which achieves AVS on-chip cloud architecture.