Construction Of SOA Architecture And Implementation Of AVS Encoder On FPGA

AVS standard is the digital video and audio coding standard possessing independent intellectual property rights and established by Audio and Video Coding Standard Workgroup of China. This standard is of high coding efficiency and international advanced level and has become the basic standard adopted in such major video applications as high definition TV, network television, video communication and so forth. AVS was approved and assigned as a national standard of the new generation of video and audio coding standard in 2006. Currently, China Unicom has utilized AVS as the IPTV standard, making AVS enter the stage of industrialization.A series of advanced technologies are applied in AVS standard to take account of two limits, processing speed and complexity, but the data are massive in coding compression and the computation speed is still high. FPGA, high in performance and flexibility, can achieve the fast processing of complex algorithms because of its high parallel computation speed and rich register resources, which is one of the best choices to implement AVS encoder.High computation speed is required because of the massive data and high complexity in AVS coding and also to meet the demand of real-time coding. In this study, a novel architecture is proposed—serve-oriented architecture (SOA) on FPGA, to achieve AVS encoder. According to the characteristics of Ethernet transmission, on-chip write-only bus (BoW) and the message access mechanism based on BoW are designed, based on which the network topology structure of on-chip write-only bus is proposed. The network topology structure of write-only bus is simple, consisting of a master processor node (Sequencer) and a certain number of slave processor nodes (Atom Components). Nodes are hitched to the bus through uniform node interface (UNI), reducing the complexity of pin interconnection of atom components. The sequencer engine is proposed and achieved to control the execution sequence of processes, the connection between the nodes adopts the message transmission mechanism of BoW bus and the communication protocol is simple.On this basis, the key algorithms of AVS encoder are achieved on FPGA in this study, including intra-frame predicdion, residual/reconfiguration, DCT/IDCT transform, quantization/inverse quantization and entropy coding. According to the characteristics of coding algorithms, the key algorithms of AVS encoder are divided into four function modules, which are packaged into atom components accessed based on messages, including image capture atom component, prediction transform atom component, encoding atom component and stream splicing atom component. To improve data processing speed, each function module is optimized by utilizing highly parallel algorithm and pipeline design method.To improve coding speed further, multiple atom components and processes are deployed into the bus and processed in parallel in this study, achieving the real-time encoding of high resolution images. Synthesized by ISE and simulated by ModelSim, the maximum clock frequency can be up to 130MHz. The real-time encoding of D1 resolution I-frame images can be implemented on Virtex-5 platform when adopting the system clock of 100MHz. Transmit the real-time encoded bit stream to the client Ethernet transmission system, decoded by decoder and displayed on player, verifying the real-time encoding ability of AVS encoder.