Research On Chip-Level Implementation Technology For Image Encoder Supporting JPEG Format

With the development of submicron technology and the continuous improvement of FPGA(Field Programmable Gate Area) chip technology, the SOPC(System on a Programmable Chip) based on FPGA attracts more and more attentions from the IC designers, because of its fascinating characteristics, such as flexible in designing, software and hardware programmable etc. However the research and the application in this field are relatively limited in China, therefore, it is very important to pursuit the research on this kind of system.Here is the main contribution of this paper:First of all, the method that is used to design SOPC based on FPGA and IPcore has been analyzed. And then the basic development conditions have been introduced, which includes the hardware structure, environment and tools for the development.After that, discussed the basic structure and characteristics of the embedded PowerPC405 processor hardcore, and implemented an embedded system based on it. A Linux operation system has been constructed on that embedded system. Combined with goal board ML403, an image encoder supporting JPEG format has been designed and implemented. At the same time, the VerilogHDL has been used to implement the DCT(Discrete Cosine Transform) which is called by the form of IPcore. In this way, it achieves higher performance.Finally,a comparison has been made among design style of encoder proposed in this paper and its pure hardware as well as pure software counterparts. The result shows that it deserves its unique advantages to accelerate a certain part of the encoder by hardware. Compared with pure software way, this method achieved higher speed, while compared with its pure hardware counterpart, the method consumed less logical resources, which improved utilization and flexibility of the hardware.