Research Of Encoding And Decoding Technologies On Digital Baseband Communication

With the development of digital communication, design of baseband transceiver indigital communication has been integrated on one SOC chip. Owing to the product ofwireless communication not only possesses the low cost and the low power, but alsocan achieve short-distance transmission. It has been used widely in digitalcommunication. Therefore, reducing the power consumption of wireless products hasbecome an emphasis of research on baseband transceiver. Importantly, the control oferror coding in the processing system of baseband is also a key part of design. Itincludes CRC, scrambling, interveaver and viterbi decoder, which have been widelyused in the practical application of communication. Especially the viterbi decoder isan important part of the baseband. The low power consumption and small area ofdesign have become the focus of research. Therefore, the study of the encoding enddecoding technologies on digital baseband comunication has a great significance.In this paper, it’s mainly about the key technologies on the module of error controlcoding in the digital communication of baseband. Firstly, it is major about the systemdesign of sending and receiving modules on baseband, and briefly describes the ASICdesign flow. Secondly, it makes a research on CRC, scrambling, interveaver andviterbi decoder which are included in error control coding. The design makes use ofthe Verilog hardware language and the top-down approach to realize the design ofCRC, scrambling, interveaver and viterbi decoder, and it makes a focus research onthe low power of (2,1,9) viterbi decoder design, it uses series and parallelcombination in four-level pipeline design. To increase working rate, with theconsideration of the implementation hardware complexity, a modified add compareselect(ACS) unit is used to satisfy its low power decoding requirment. Additionally, inorder to increase the efficiency of decoding and decrease the latency of decoder, amethod of path mutual eliminating is employed in the design. Implemented by TSMC0.18μm standard CMOS technology, synthesized with Synopsys’ Design Compilerunder1.62V and125℃, analyzed with placement and route with encounter, thechip’s highest speed is about50MHz, the area is0.212mm2, and the power is22.9mW.