The Design And Verification Of Key Modules In PCI Express 2.0 Physical Layer

Because of the bottleneck of shared parallel architecture and performance, PCI bus has restricted the rapid development of computers and peripherals. The third-generation I/O bus technology PCI Express, released by Intel, is a revolutionary upgrade of PCI bus protocol. PCI Express belongs to high-speed, serial point to point and dual channel transmission, with high cost-effective, high scalability and high flexibility characteristics. In the PCI Express layered protocol, physical layer bears the data on link transmission and reception tasks. It has a certain value and significance in its study.In this dissertation, current domestic and foreign research status in PCI Express bus is introduced firstly. Then the basic concepts of PCI Express bus, such as link, bandwidth, topology, device hierarchy, and packages are described. Moreover, the function and structure of the transaction layer, the data link layer and the physical layer, and the process of data transmission between PCI Express layers are analyzed in brief. The research of the physical layer in the PCI Express 2.0 protocol specification, with successful implementation of the main functions of physical layer based on FPGA are also presented.The structural module in physical layer with top-down design approach, and complete the key modules RTL design by Verilog HDL are designed, such as multiplexing and de-multiplexer, scrambler and descrambler, 16B/20B encoder and decoder, elastic buffer, channel alignment, etc. Then modules and system functional simulation are processed. Finaly, RTL-level synthesis with logic resource usage status is given. The implementation based on Xilinx FPGA development board VC707 is performed. According to the loopback test results, the physical layer with 4 channels satisfies the PCIE agreement.In the end, the shortcoming in design and the further research direction are pointed out in this dissertation, and the suggestions for improvement are given.