The Design Technique Of High-speed And Low-power Single-rail MOS Current Mode Logic Circuits

MOS Current-Mode Logic (MCML) is usually used for high-speed applications, due to thepower consumption of a SRMCML gate is related to the source voltage and bias current. Thedesign methods of the basic single-rail MOS Current Mode Logic (SRMCML) circuits arepresented by analyzing the working principle, performance parameters and the design parametersof dual-rail MOS Current Mode Logic (DRMCML) circuit in this thesis. A single-rail realizationscheme of MCML circuits is described, which can avoid the devices in series configuration, sincetheir logic evaluation block can be realized by only using MOS transistors in parallel. Besides, theSRMCML circuits reduce the delay, so the power-delay product of the SRMCML circuits issmaller than the DRMCML circuits. Otherwise, near-threshold SRMCML and power-gatingSRMCML are proposed in the thesis for reducing the static power dissipation. The thesis mainlydivided into the following several parts.The first part is introduced the basic DRMCML circuits and analyzes the working principle,performance parameters. In addition, the complex combination and sequential DRMCML circuitsare designed in this part for prepare to design the SRMCML circuits.The second part is introduced the basic SRMCML circuits and analyzes the working principle,performance parameters according to the DRMCML structure. Otherwise, the SRMCML1-bit fulladder,4-bit carry look-ahead adder and mode-10counter are designed. Besides, the powerdissipation, delay and power-delay product of SRMCML circuits are compared with DRMCMLand static CMOS structures.In the third part, the method of near-threshold is used to the SRMCML circuits for reducingthe static power dissipation. The analysis for minimum operating supply voltage of MCML circuitsis addressed by the performance optimization algorithm for near-threshold sequential circuits basedon SRMCML. Otherwise, the performance parameters of SRMCML circuits are compared withDRMCML and static CMOS circuits. The results show that the near-threshold SRMCML circuitscan obtain low delay and small power-delay product.In the fourth part, a power-gating technology for SRMCML circuits is presented. Theequivalent model for calculating energy dissipations of the power-gating SRMCML circuits isconstructed. Besides, the thesis builds the relationship between the size of high-threshold PMOStransistors and the power-gating SRMCML circuits. At last, the power dissipation comparisons among power-gating SRMCML, conventional single-rail MCML, and static power-gating CMOScircuits are carried out. The power dissipation of the proposed power-gating SRMCML circuits isthe least among the three above mentioned structures.