Design Of Sram For Hardening To Multiple Node Upset

With the rapid development of integrated circuits(ICs), the manufacturingprocess scales into the nanometer regime and IC systems become more and morevulnerable to ionizing radiation from terrestrial and cosmic sources，especially thesingle event upset (SEU) effect. As the industry develops, the SRAM occupies anincreasingly important position because of its high speed, low power consumption andexcellent performance. But it is also the most sensitive to the SEU, so the industry hasbeen researching for the effective solutions to hardened SRAM.The radiation hardening solutions, such as process-level, layout-level,architecture-level and circuit-level solutions, and the mechanism of are firstlyintroduced. Because that there are few hardened memory cells immuning to multiplenode upset(MNU), a128x8bit SRAM, which immuned to MNU, has been designedwith improved DICE, that is TDICE, validated in SMIC65nm technology in thispaper. Then the performance of TDICE is studied in detail and SMIC65nm standardcell library built flow is studied deeply. According to the design rules of standard celllibrary, the TDICE is designed to be a standard cell and verifications show it can beused by EDA tools. Besides, The peripheral combination circuits of SRAM and theirfunction simulations are explained in detail, and the construction for the whole circuitof SRAM is implemented. The peripheral combination circuits mainly includedecoder circuits, sensitive amplifier, write-control circuit and data input/output circuit,and so on. The simulation results show the SRAM can work correctly.Finally, the layout of each circuit model and SRAM are implemented usingSMIC65nm technology, and the post simulation results improve that the designedSRAM can implement read and write operations rightly under1.2V supply voltageand100MHz with MNU immunity.