Design Of On - Chip ADC / DAC Module Test System Based On

As the IC manufacturing technology becoming more and more complex, the difficulty and cost of chip testing keep increasing. For controlling output chip quality, ATE (Automatic Test Equipment) based DFT (Design for Testability) testing technique is widely used by semiconductor manufacturers. The performance test of high-precision high-speed on-chip ADC/DAC IP is a difficulty in post tape-out chip testing domain. Traditional testing methods still have many drawbacks, such as high cost, low speed and low automation.This thesis is carried out in Marvell Semiconductor Limited, Video ASIC design Group, aiming to establish a FPGA on-chip ADC/DAC performance test system, for optimizing on-chip ADC/DAC dynamic performance test process, reducing test time and test cost. This test system is implemented on an emulation board of Altera FPGA, utilizing onboard Stratix IV EP4SE530F1517 FPGA device and onboard high-precision ADC/DAC chip. Two test loopbacks are built on the FPGA emulation board, separately for the on-chip ADC module under test and the on-chip DAC module under test. On FPGA, signal generator module, control module and performance checker module are designed and implemented. The signal generator module uses CORDIC algorithm to generate high-precision sin-wave. The performance checker module is designed to evaluating dynamic parameters, based on FFT analysis method. Dynamic parameters, SNDR, SNR and THD, are obtained by executing a test. The logic designed on FPGA follows pipeline design principal. Sample processing and frequency analysis is done in real-time, without using any extra buffering resource. Compared to traditional software based analysis method, test time is saved using this test system. Compared to traditional ATE (with analog channel and AWG) based test method, test cost is reduced and flow automation is improved, when using this test system.