Research On Key Issues For Testing Network On Chip

With the development of integrated circuit manufacturing technology, transistor feature sizecontinues shrinking, the number of cores integrated on a single chip increasing rapidly, thetraditional bus architecture of system-on-chip can’t meet the needs for the development of multi-coreinterconnection. Because of its high communication efficiency and strong scalability,network-on-chip has become the mainstream of design of the future multi-core interconnectionarchitecture. However, since the network-on-chip using a grid-type network architecture in which isembedded a large number of homogeneous or heterogeneous IP cores and complex communicationcomponents, its test faces a large number of issues such as large test data volume, low test efficiency,complex test scheduling and difficult fault location and so on.This thesis analyzes features for testing the network-on-chip and focuses on improving the testdata compression ratio, enhancing test parallelism, reducing test time, optimizing test schedulingalgorithm and narrowing the scope of fault location and other aspects. We do the research work onsolving several key issues for testing network-on-chip.The main work and innovation are depicted as follows:(1) This thesis presents a test data compression method and the corresponding decompressionmechanism based on variable-length data blocks and statistical correlation for solving the issue oflarge amount of test data during the process of testing network-on-chip. In order to achieve efficientdata compression, we determine a data block with the best correlation as a reference to the testvector data blocks.(2) A new test optimization mechanism is proposed to improve the network-on-chip testparallelism and test efficiency in respects of test data transmission parallelism and test applicationparallelism. By using the sequentially shifting matching algorithm, the sharing of heterogeneous IPcores’ test data sets is achieved. The test time is reduced effectively by folding partitions, multicastinjection and classified receiving.(3) Considering the time and power factor synthetically, this thesis presents a highly effectivetest scheduling algorithm. We select the number and position of I/O ports to improve the efficiencyof test resources usage under the premise of minimum test cost, meanwhile, all the IP cores’ paralleltest time is shortest by using the test scheduling algorithm.(4) For the shortage of pseudo-exhaustive test strategy: large test data volume, being given awide range of error and unable to accurately locate the error position and other issues, we propose apartition test method for communication architecture of network-on-chip. The communicationarchitecture between the various partitions can be tested concurrently by partitioning the network. In addition, this thesis also designs a packet-based traceback error localization method that combinesmultiple packets error information and uses the elimination method to accurately give the faultlocation in the communication architecture of NoC.