| With the development of the technology of SOC and IP nuclear, phase-locked loops are used as clock electric circuits in the wireless telecommunication and microprocessor electric circuits more and more popularly as basic ASIC macrocells. Nowadays new requests have been proposed for the synchronization in and between segments, especially in the rapid development of modern telecommunication industry such as honeycombtelephone(Cell Phone) and bluetooth technology(Blue Tooth). The research of the working frequency, power loss, characteristic of phase noise, lock speed, chip area, processing cost and the design cost of PLLs is also becoming the important focus gradually.In this paper, we design the PPL circuits based on a clock recovery system. The purpose of this design is to use PLL(Phase Locked Loop) and DLL(Delayed Locked Loop) to realize the function of clock recovery block of within the USB2.0 (Universal Serial Bus) Transceiver Macrocell. In this block, a 12MHz sin signal from external crystal is synthesized into a 480MHz clock signal through the PLL clock generator, and the DLL can recover the clock signal from external date wave according to the local clock signal. At first we introduce the research background of our topic, discussing the history, development and the status of phase-locked technology. And we also describe the details of the principle and main features of PLL. Then, based on these theories, the electric-circuit units of the PLL module and the DLL module are designed in turn. At last, the phase-locked circuits in the USB2.0 UTM are finished and the design results are showed.This design is fabricated in a 2.5V, 0.25μm first silicon CMOS process, simulated and emulated under the HSPICE platform. The simulation result indicated that, the lock time of PLL circuits is only 2.4us, the power loss under 480MHz working frequency is only 12mW, and the frequency spectrum outputted presents a high purity, which shows the characteristic of high speed, low power loss and low noise. The lock time of DLL circuits is only 2.4ns, presenting the merit of a high speed and adjustable bandwidth. During the design we also perform the design of PLL territory, and we attain the final territory through the territory withdrawing and the simulation and emulation. Therefore, this design of phase-locked circuits can perform a good function, which is able to cater to the requirement of the development of high-speed circuits. |
