Design of noise-robust clock and data recovery using an adaptive-bandwidth mixed PLL/DLL

As the continuing technology scaling keeps increasing the maximum on-chip clock frequency, the demand for the high-speed link that bridges the faster on-chip world and slower off-chip world is rapidly growing. The challenges are stronger than before with more functions being integrated into a single chip, which has become a complicated mixed-mode System on Chip (SoC) design. The performance of the link system greatly depends on how well the noise is managed in the system. Unfortunately the noise conditions in a highly-integrated SoC are usually difficult to predict before chip fabrication and vary quite a lot among different systems. The noise problem is particularly more troublesome on the receiver side than the transmitter side, because the receiver usually consists of more circuit blocks than the transmitter. If one can design a noise-robust receiver that can adapt to various noise conditions, such a macro can be used within a variety of systems and therefore reduce the cost of custom design. This dissertation presents a receiver design that can adjust itself under time-varying noise conditions in order to minimize jitter and achieve optimum performance.; This dissertation first describes an adaptive-bandwidth mixed PLL/DLL (MX-PDLL)-based multiphase clock generator to achieve the optimum jitter performance under different noise conditions. The MX-PDLL uses a phase mixing interpolator to merge traditional PLL and DLL loops into a single loop. The resulting wide range of bandwidth adjustment enables this mechanism for adapting across different noise conditions to minimize jitter.; The dissertation then introduces a new clock and data recovery (CDR) architecture using this MX-PDLL clock generator in a receiver. This CDR uses a digitally-controlled phase rotator to shift the phase of the reference clock that feeds into the MX-PDLL to track the phase and frequency of the data. By tuning the bandwidth of the MX-PDLL, the CDR can find the optimum bandwidth setting under different amount of power supply noise, reference clock noise, and digital control-induced quantization noise to minimize clock jitter and thereby enhance performance.; A prototype chip was fabricated in a 0.18mum CMOS technology, and all the measurement results verify the above claims.