Research Of Embedded Memory MBIST Based On65nm Process Technology

Nowadays, evolution of LSI mainly reflects in two aspects, the increase in the scale of the circuit design and the improvement of chip manufacturing process. Enlarging of IC design scale lengthens design period, which is counter to market need, so people gradually begin to carry on IP(Intellectual Property) design of some modules with specific function in the circuit system, so that the IP which is designed in advance can be reused in complicated circuits design every time, which is called IP reuse design, which greatly decreases the complexity of circuit design, shortens the period of chip design, and make SOC(System on Chip) design based on IP reuse technology become mainstream design methodology in today’s IC design.With integrated circuit scale enters the era of ULSI, the cost of chip test becomes inignored, and sometimes even surpasses R&D cost, so designers begin to take test into consideration in the early stage of chip design, which largely decreases the complexity of chip test, which is called design for testability technology. Memories, as modules for storing data, are indispensable parts in the circuits, and SOC chips based on IP reuse technology integrate even more memories. Besides, memories are array structure constituted by storing cells, and their high density and storing function make test of memories different from normal logic circuits, so memories embedded in SOC chips are needed to be tested solely during the test of whole SOC chip.Built in self-test (BIST) is a widely used method in design for testability of memory. It provides memories the excitation signals for test with a reasonable area cost, then do read or write operation to the memory cell, finally compare the data stored in memory with expectation to detect the memory fault.The test circuit isn’t the same due to different process and testing requirement. This paper studied about the test circuit of memory under65nm process, including memory test algorithm and memory stability testing mainly. For the study of memory test algorithms, firstly, this paper modeling the behavior of memory fault, and provide the test method for each fault. Secondly, this paper introduce some classical March algorithm, finally this paper propose a new algorithm which based on the classical March algorithm, then make a comparison between the new algorithm and the classical algorithm. Besides, the paper defines a new test circuit, and introduces its operating principle, and the corresponding testing program, at the last, this paper analysis the advantages and disadvantages of the two kinds of MBIST.