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Research On The Two Dimensional Semi-analytical Of Fully-depleted SOI MOSFET In Sub-threshold Region

Posted on:2018-07-26Degree:DoctorType:Dissertation
Country:ChinaCandidate:H ChangFull Text:PDF
GTID:1318330515979585Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the constant development of semiconductor technology,the feature size of MOSFET has been reduced to nanometers,which greatly improves the performance of devices and integrated circuits.However,the increasing small size effect seriously affects the further development of devices.To reduce the influences of the small size effect,novel deviee structures,materials and process technologies have been proposed such as the Silicon-on-Insulator(SOI)MOSFET,the high-k material and the ultra shallow junction technology.Besides,in the process of integrated circuit design,the high-speed and accurate device model have important significance to shorten the development cycle and improve the performance of integrated circuits.Thus,small sized devices should be re-modeled to accommodate the development of semiconductor technology.In this thesis,relevant researches were performed based on the background,the primary work is as follows:(1)Firstly,the development of semiconductor devices and SOI technology are demonstrated in this thesis,and then the advantages and disadvantages of two classical SOI MOSFET models are emphatically analyzed.Secondly,a semi-analytical method is proposed to establish the SOI MOSFET model.Finally,through the analysis of relevant theory,the feasibility of the two-dimension model established by semi-analytical method is investigated.(2)With the reduction of the feature size,the two-dimensional field effect of buried oxide layer has an increasingly influence on the front surface potential.Therefore,during the process of establishing the potential model,the Poisson equations of the gate dielectric layer,the silicon film and the buried oxide layer should be confirmed.Firstly,we introduce three rectangular sources of the gate dielectric layer,silicon layer and buried oxide layer to establish the Poisson equations of three regions,and then verify the corresponding boundary conditions.By the separation variable method,the two-dimensional analytical expression of potential is established,which contains the undermined coefficients.Then,based on the characteristic function expansion method and the connective condition,a matrix equation containing the undermined coefficients is presented.Finally,the two-dimensional semi-analytical model of SOI MOSFET potential is established by substituting the undermined coefficients into the expressions of the potential.Based on this,according to the definition of threshold voltage and bisection algorithm,a threshold voltage model of SOI MOSFET based on surface potential is established.(3)The thickness of gate oxide layer will gradually decrease with the further reduction of device size,which causes a series of problems such as tunneling current.To solve the problem mentioned above,the high dielectric constant material is applied as the gate dielectric.First of all,the high-k gate dielectric material and its fundamental characteristics are elaborated in this thesis.Then,the solution of the potential distribution of the high-k SOI MOSFET is established by using the modeling method established in chapter 3.After that,the semi-analytical method and the characteristic function expansion method are used to derive the two-dimensional semi-analytical model of potential.Based on the established potential model,a threshold voltage model is deduced.Finally,the potential model and the threshold voltage model are verified by simulation.(4)With the diminishment of device size,the short channel effect is increasingly significant.The ultra-shallow junction technology is adopted to reduce the short channel effect,while the smaller leakage source junction depth will lead to an increase of the drain/source parasitic resistance(RSD),and further restrict driving ability of the device seriously.Thus,it has important significance to accurately evaluate the value of RSD for device characterization and circuit simulation.Based on the principle of MOSFET,a definite solution of potential is proposed by introducing one rectangular source in drain/source region.Then,by using the variables separation method,Fourier expansion method and the integral equation,the potential distribution of source/drain region and two dimensional semi-analytical model of RSD have been obtained,calculate the relationship between the RSD and device geometry,the solution is a special function for the infinite series expressions.The results of calculation and simulation show that the model has high precision.In summary,the novel two dimensional model of potential,threshold voltage and RSD are proposed by using the semi-analytical method in this thesis and verified by the Silvaco software.The comparison results show that the proposed models have higher accuracy,the parameters in models have definite physical meaning.In addition,this model,which can be directly used in the circuit simulation,has the characteristics of its expression without fitting parameter and small calculating amount.
Keywords/Search Tags:semiconductor technology, small size effect, SOI MOSFET, parasitic source/drain resistance, semi-analytical method
PDF Full Text Request
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