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The Study Of The Modeling Of SOI And MOSFET Based On Semi Analytical And Semi Empirical Methods

Posted on:2019-05-21Degree:MasterType:Thesis
Country:ChinaCandidate:J G YangFull Text:PDF
GTID:2348330542993907Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Early modeling methods for SOI MOSFET devices mostly establish Poisson equations in silicon films,then corresponding partial differential equations are solved through boundary conditions.However,these models contain a number of mutually coupled implicit equations,it takes a lot of calculation to solve those equations,which is clearly inefficient for modeling.This thesis presents a two-dimensional semi analytical model for the surface potential and threshold voltage of a SOI MOSFET with high k + SiO2 gate.The generalized Fourier transform is used to simplify the Laplace and Poisson equations in the model.This method can not only better model nanoscale fully depleted SOI MOSFET devices,but also analyze the properties of various gate dielectric materials.The ultimate goal is to optimize or predict the performance of the device.Most of the extraction methods of MOSFET source/drain resistance are based on the channel resistance method.In this thesis,a new two-dimensional semi empirical model is proposed to summarize the MOSFET source/drain resistance.The main idea comes from the formula R=pL/S that is used for calculating the resistance value of the conductor,an expression of MOSFET source/drain resistance with three parameters is derived by theory.The contents of this article are as follows.Firstly through the analysis of advantages,disadvantages and the development of fully depleted SOI MOSFET and bulk silicon MOSFET,this thesis leads to the modeling objects and modeling methods.The methods are two-dimensional semi analytical model for threshold voltage of fully depleted SOI MOSFET and high k +SiO2 gate of SOI MOSFET and two-dimensional semi empirical model for resistance of planar MOSFET source/drain.For the analysis of the fully depleted SOI MOSFET model,the device model is firstly partitioned reasonably according to the internal electric field and the charge distribution.Each partition is analyzed one by one,then the internal potential equation is established.The front gate dielectric layer and buried oxide layer are all oxidation layers,and there is no free charge inside,so this partition satisfies the Laplace equation.Because the silicon film has a fixed charge,it satisfies the Poisson equation.After determining the equation and boundary conditions,the expression of the surface potential of the front gate and the surface of the back gate is expanded by Fourier transformation.Finally,the partial differential equations in each region are transformed into multivariate linear equations.The solution of the linear equations is quickly obtained by the elimination of the main elements of Gauss column,then the solution of model equations is obtained.Based on the modeling method,this thesis can not only find the surface potential of the front and back gate of the model,but also find out its overall two-dimensional potential diagram.The two-dimensional potential contours obtained in the model is compared with the device simulation,the error of the result is small,which indicates that the semi-analytical method is accurate.In order to show the novel features of the model,the threshold voltage model and the surface potential model are also studied in this thesis,It includes the influence of the thickness of silicon film,the influence of doping,the thickness of the front gate and the thickness of the back gate.Through comparing this model with the ATLAS tool,the calculation result shows that the calculation result of this model is correct and accurate.The performance and parameters of fully depleted SOI MOSFET can be predicted completely.In order to verify the effect of this model on the short channel effect,the DIBL effect of two models at different drain and source voltages and channel lengths is discussed in this thesis.Finally,based on the most classical channel resistance extraction method about the bulk silicon source/drain resistance,by analyzing the way of carrier movement and the derivation of integral median theorem,this thesis puts forward a parameter expression of source/drain resistance.The expression is simplified by multiple linear regression,and the parameters in the expression are finally determined by the channel resistance extraction method.Finally,the results of the model are compared with the ATLAS results for illustrating the rationality and correctness of the semi empirical model.
Keywords/Search Tags:SOI with high k + SiO2 gate, Front gate surface potential, Threshold voltage, Semi analytical method, Resistance expression
PDF Full Text Request
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