The Acceleration Method Research For Small-delay Fault Simulation

In order to guarantee the correctness of the integrated circuit timing, get the rightresponse to the output within the specified time, need to delay testing for integrated circuits.With the IC manufacturing process into the nano-scale，the fault size of delay fault in circuit isless than one clock cycle. If through a short path, the fault may escape, but perform aparticular function may spread through the long pathway, resulting in failure. The other hand,in the future, these defects will rapidly increase the chip rapid aging, and ultimately lead tochip failure. With the IC frequency increases, the influence of small delay fault in circuit isincreasingly clear, and testing small-delay defects become increasingly important.Fault simulation is the indispensable step in the test, used to support test generation andevaluation of the quality of the test set. Small-delay fault testing methods need to use thesimulator supporting research, small-delay simulator is still in the preliminary stage, and thereis still much room for improvement in the speed. Therefore, study the small-delay faultsimulator accelerated strategy and develop more high-speed small-delay fault simulator hasan important significance.This paper in-depth study small-delay fault of the features to identify the critical path ofthe stuck-at-fault in the small-delay fault simulation, critical path identification of the smalldelay fault simulation. Combination of the critical path tracing algorithm proposedacceleration method based on the critical path delay. Newly developed simulator experimentsshow that the identification of the critical path in the simulation of a small delay in thememory overhead little change in the circumstances has access to the more obvioussimulation speed upgrade.Based on the critical path in the small delay fault simulator, and on the basis of analyzingthe disadvantage of critical path tracking method, make improvement, proposed an integratedsmall-delay simulation method. This paper proposes a new simulation method for small-delayfault, which is based on the combination of waveform simulation and critical path tracing.Starting from fan-out stems, the simulation process is carried on by backward tracking andforward grouping. Through the use of circuit partitioning and critical path tracing, theproposed method reduces the consumption on unrelated fault simulation. The experimentalresults on ISCAS89circuits show that the proposed method has obvious advantages in termsof applicability and simulation speed compared with the existing small-delay fault simulator.