Research On Simulation Methods Based On GPU For Small Delay Faults

Integrated circuit test is an important part of its production. With the rapid development of VLSI, the design of integrated circuits(IC)scale increasing and the feature size shrinking, the test about integrated circuit become more and more difficult. Especially after the IC process enter into the nanometer era, the phenomenon of crosstalk noise, process variations, power-supply noise bring many small delay faults in the circuits, which affect the reliability of the chip seriously. So small delay fault detection becomes essential. Fault simulation is the basis for IC test, existing small delay fault simulation methods are basically based on the serial simulation, which takes long time. So there is still much room for improvement in the speed. Therefore, studying the small-delay fault simulation accelerated strategy and developing more high-speed small-delay fault simulator has an important significance.In recent years, GPU has been used to accelerate the programs of intensive computation in many areas and has achieved very good results. This paper introduces GPU into small delay simulation and mainly discusses how to use GPU to accelerate small delay fault simulation. The main work includes the following two points:The small delay fault simulator based on the critical path tracing algorithm is implemented on the GPU. This paper studies the features of small-delay fault in-depth to identify the critical path. In addition, circuit is classified and divided into many blocks. In the FFR, critical path tracking technology is used to simulate then the faults will be stored at fan-out. These faults are parallel propagated to PO by the means of multi-thread. The experimental results indicate that the approach is on average15x faster when compared to the small fault simulation engine based on critical path tracking technology.Based on simulation of gate, the techniques of fault-free circuit wave simulation and the techniques of fault circuit wave simulation, this paper proposes a new GPU-based small delay fault simulation acceleration policies. The circuit is pre-processed, the processes include classifying circuit, transferring fault table patterns> event-list array to GPU. The new small delay fault simulation acceleration policies simulate gates by level. Every level corresponds to the event-list array obtained by using event driven algorithm. Then make the best use of the GPU’s characteristics of multi-thread to simulate many gates each time. The experimental results show that our approach is on average40x faster when compared to the traditional fault simulation engine.