Research On Small-delay Test Pattern Generation And The Method Of The Critical Path Selection

With the deepening of the dimension size of integrated circuits (ICs) technology, power supply noise,process variation, crosstalk effects and metal interconnects between the resistive open and short bring a great deal of uncertainty about path propagation delay, we call this uncertainty skew. The presence of delay deviation will not only affect the performance of the chip, but also the reliability and service life. Skew of the resistive open and resistive short between the metal interconnects is particularly evident.The paper proposed two method for the small delay defect detection, its main work and innovation is as follows:Firstly, Improve the fault coverage by adopting the different Sensitization criterion for Faster Than At-Speed Testing. Test generation method for the small delay defects(SDDs) not only requires low algorithm complexity,but also more possibility to detect small delay. Faster than at-speed testing avoids to detect the longest sensitization paths for poor efficiency.It requires test patterns to be delicately classified into groups according to the delay of sensitization paths, and each group is managed to be applied at certain clock frequency,then adopted a path selection method to identify a certain length of paths quickly and accurately, which could achieve high test quality.At the same time,the paper proposed that choosing single path sensitization criterion for short paths and nonrobust sensitization criterion for the critical paths to test,the experiment to reference circuit indicated that could improve transition delay fault coverage(TDF) of the nodes who Contain small delay defects at the cost of a little of time compared with adopting single sensitization criterion.Secondly, during the timing-aware automatic test pattern generation,under the condition of the consideration of the impact of the delay deviation, the paper proposed a method of searching critical paths based on the statistical timing model,which improved the efficiency of searching critical paths.We must find the longest path in the circuit to detect small delay defects for timing-aware automatic test pattern generation, that is the critical path. Generally static timing analysis is adopted to search critical path, which supposed the delay of the logic gate was fixed at a constant value in the circuit, but in fact,it will normally be subject to a certain distribution because of delay fluctuations. Therefore, the critical paths obtained by static timing analysis are only a part of the longest path in the circuit, and some path maybe become the longest path under some condition.The paper proposed a method of reducing circuit scale to improve the search efficiency based on statistical timing model,The experiment indicated, which could obtain the critical path effectively and rapidly.