Research On Fault Simulation For Delay Testing

With the development of production technology, the feature size of VLSI gradually decreases and some new types of detects emerges. These defects have a common performance that they change the delay of circuits. Thus they are referred to delay defects. How to make an effective delay testing is common concern in both academia and industry. Now delay testing has become a core part of production test, a hot issue in the field of IC testing. Using fault coverage obtained through fault simulation is a mean of assessing test quality. Based on transition fault model, the paper proposed three simulation methods to assessing delay testing:Firstly, a transition fault simulation method for sequential circuits has been proposed. Based on an existing algorithm, it quantifies the fault size with clock cycle. The fault simulation process is accelerated by using parallel simulation strategy and fault selecting strategy. Experimental results show that the proposed method is faster than the original method.Secondly, a fault simulator on the basis of uncertain transition fault model has been implemented. It is not guaranteed that using the propose transition fault simulation method can detect a delay defect with an arbitrary defect size, so we implements this uncertain transition fault simulator. Uncertain size summarize the behavior of all fault sizes, i.e. fault size of 1 clock cycle,2 clock cycle,3 clock cycle and so on. The experimental results show that the fault simulator has shown the expected behavior, it gives a range of coverage, which can describe the test vectors' capability of detecting a delay defect with an arbitrary defect size.Thirdly, small delay fault simulation for sequential circuits has been presented. In recent years, small delay defects have become a hot issue in delay testing. Previous test evaluation criteria, fault coverage, can not fully represents the quality of small delay testing. Statistical delay quality model has become new criteria to assess the small-delay testing. It shows that the detection of a small delay fault has something to do with the length of sensitive path. In transition fault test, the fault don't have to spread out along the longest path, so some small delay fault may be escape from the current tests. Based on the transition fault model, we propose a waveform simulation to detect test escape. The delay distribution in the CUT is considered. The results suggest that it can detect test escape, which can not be detected in tradition transition fault simulator. So it may give some useful information to ATPG, and then ATPG can generate some better test patterns to improve the test quality.