Research And Design Of The Des Encryption Chip Based On Resource Optimization

DES(Data Encryption Standard)was officially approved to be the standard encryption by ANSI in1977. It has been encountered varieties of attacks and undergone long-term challenge since it had been opened to the public. Now it’s one of the most widely used block cipher.In this paper, on the foundation of analyzing the algorithm mechanism, a kind of optimal resource scheme is proposed. By setting only one round circuit, encryption is completed by using this circuit16times. The sub key generation part of the circuit is based on pure combinational logic. To simplify the design of the control module, finite state machine is adopted. So the hardware resource consumption is reduced greatly.The development platform of this design is QuartusII10.0of Altera Corporation. And the used simulation software is ModelSim-Altera6.5e. This design is described by Verilog HDL and passed RTL simulation and static timing analysis. At last, the design is implemented on the FPGA chip:Cyclone Ⅱ EP1C12Q240C8. The results are that:this design only uses364logic elements and2048memory bits. The highest clock frequency is up to56.57MHz and the speed of encryption is up to212.98Mb/s. In order to reduce the power consumption, gated clock is adopted and the power of the system is54.56mW.