Design And Implementation Of A CAN Controller Soft Core Based On FPGA

The technology of field bus is one of the hottest technologies in the automatic control field. CAN bus (Controller Area Network) is one of the most important field bus, which mainly work in data link layer and physical layer. It 's fully accordance to the OSI system. CAN bus is a fully digital, multi master and asynchronous serials field bus. It has the feature of message filter, error management system, high speed and long distant communication, and the easy interface to the application layer. Nowadays, CAN bus is widely used in auto industry, aviation industry, automatic control, and the application in other field is rapidly developed.Now chips available in the market are customized with all kinds of standards, so the key to design CAN bus is how to design and use them. However, these CAN controller chips have fixed interfaces, poor universal use, can not be compatible and easily integrated into existing embedded systems. If we hope to implement additional features, we need to build external circuitry. To address above short comings, we can design a CAN controller soft core, and build CAN bus system in a single FPGA. Meanwhile, we can integrate other digital circuit in the remaining resources of the FPGA to reduce the number of peripheral chips.The main purpose is to complete the front-end design of CAN controller using FPGA.That means to complete the RTL-Ievel design of Data Link layer and Physical layer in CAN protocol by using Verilog HDL, and to achieve its function, then to evaluate the design through the simulation on the platform Spartan 3E.Firstly,we analyze CAN 2.0 Protocol.Secondly, after analysising the existing CAN controller chips we determine the CAN controller structure of this paper, and split the entire CAN controller into several modules which are independent but associated with each other, including Interface Management Logic(IML), Registers and CAN_Core.Their function and principle are introduced too.IML provides two optional interface mode, including WISHBONE SOC and SCM, which meet diverse interface design of equipment to CAN bus. Registers'design refers SJA1000. CAN_Core consists of two parts: Bit Stream Processor(BSP), including receiving part, sending part, bit stuffing, CRC checking, acceptance filtering, error management logic; the second is Bit Timing Logic(BTL), including bit timing and synchronization.In simulating, we suppose the clock cycle to be 10ns,and under this condition, the modules are found to meet the design requirements.In other words,we have laid the foundation for incorporating more functions into CAN controller based on FPGA.