Design And Verification Of Reusable SPI IP Soft-core Based On Verilog HDL

With the rapid development of integrated circuit technique, System-on-Chips (SOC) technology has become the mainstream technology of IC design based on the on-chip bus technology and the IP technology. However, the current development of SOC is also facing two major challenges:multiplexing and interconnect of IP core. Therefore, the research of IP reuse technology has important significance for the development of SOC. SPI, launched by Motorola Company, is a kind of high-speed, full-duplex, synchronous communication bus. More and more IC chips are integrating this protocol because of its simple structure and less signal lines. So in this thesis, we designed two IP soft-cores of SPI protocol, which are more flexible, reusable and configurable. The design is fully meeting the requirements of the development of SOC technology and has a very high significance and practical value for popularization and application of SPI in the industry.According to Top-Down design theory, we designed two kinds of reusable IP soft-cores of SPI protocol. One of them was based on microcontroller protocol and mainly focused on the function of SPI host. It could communicate with 8 SPI slave, and can be set the rate and mode of transmission. At the same time, the module of transmitting logic and receiving logic are designed separately to provide double buffering mechanism for each part. In design, we divided the sub-module, present a complete module and signal connection diagram as well as detailed registers settings. Then described the realization of the key sub-modules using Verilog HDL, including the design concept, the design process and the solution of typical problems of several important modules such as microcontroller interface, Clock Logic and Transmit/Receive Logic, etc.Another IP soft-core based on Wishbone bus was designed for multiple devices by Parameterization method. It could automatically identify the master/slave devices between the devices number of 4,8,16, and arbitrate the control right of same slave device between multi-masters according the setting of slave’s priority level. We analyzed the design objectives, divided its sub-modules and illustrated the register Settings. Finally, described the realization of the IP soft-core using Verilog HDL, including the design ideas and the function and code design of important modules such as Wishbone interface, Clock Generate, and internal control register.Based on the completion of design, we carried out RTL function simulation and timing simulation of the two IP soft-cores using mainstream simulation software Modelsim and QuartusII. The results showed that the design of two SPI IP soft-cores is correct, and all the functions meet the design expected. The simulation process passed successfully.