A Verilog Precompiler For Interactive Optimization Of IP Core Design

SV+is an interactive compiler that makes circuit designer do trade-ofs betweenresource consuming and time cost easily, without rewriting the source code. A setof succinct SV+syntaxes are proposed in this work. They can be used to embed withHDLs[1] to describe the re-confgurable parts of a circuit. Users have chances to selec-t optimization options during the compiling process. The compiler generates VerilogRTL codes, depends on these choices. And for diferent optimization choices, the cir-cuits vary in architectures besides in time and resource. SV+syntaxes can describereconfgurable circuit structures in mathematical or functional level, so designers areliberated from putting much efort on concerning about module scheduling and wireconnection. Unlike other circuit compilers, for example DFT compiler[2], that workon single kind of algorithms, SV+syntaxes can be used in a range of Verilog programsas long as there are any reconfgurable structures been explored in SV+system.