Design And Implementation Of Reusable IP Core Of SPI On Besis Of Verilog HDL

The SPI put forward by Motorola Company is a full-duplex, synchronous, serial data link that is standard across many microprocessors, microcontrollers, and peripherals. It enables communication between microprocessors and peripherals and/or inter-processor communication. The SPI system is flexible enough to interface directly with numerous commercially available peripherals, and it also has some excellences such as it can be configured flexibly and it has a simply structure, and so on. Wishbone bus is a On-Chip-Bus protocol released by the company of Silicore. Its structure is very simple, flexible, and it's completely public, completely free, so it acquires numerous supports. Along with the development of System-On-Chip, its design needs reusable IP Core. So this article mainly introduces particularly how to describe the SPI with Verilog HDL in RTL's level, then simulate and verify it with EDA softwares. After then, we probe into the Reusing Methodology's application in modern circuit system. At last we finish a reusable SPI IP core based on Wishbone bus for SOC, to accomplish the correspondence between SOC and peripherals through the SPI. In the design, programme is hiberarchy, and the spi_master's design and the spi_slave's design are finished in this paper, and also have a testbench programme to check SPI function. Finally, the design achieves the expectant target and the SPI protocol's requirements, and the spi_master module is a independent, reusable IP Core for SOC. Then, this text will carry on the analysis to this design from the aspects, such as function, speed, area and cost and so on, and sum up experiences that acquired in the integrated circuit design.