Design Of A Low Power Digital PLL-Based Clock Generator

From the concept of Phased Locked Loop (PLL) proposed, it is widely used in electronics and communication field by its excellent characteristics, such as Frequency Synthesizer, Clock Data Recovery circuits. However, modern multimedia communication market is changing so fast that people propose much more stringent requirements for Phased Locked Loop. Therefore, the design of Phased Locked Loop is facing new challenges:on the one hand, the new requirements of Phased Locked Loop become more stringent, such as higher frequency, multi-bandwidth, lower phase noise; on the other hand, low cost and low power consumption are becoming the focus of the development of modern multimedia communication. In a word, the design of Phased Locked Loop mainly focuses on low cost, low power and high performance.Under the background, this paper designs a PLL-based Clock Generator, which has the characteristics of low power and all digital.On the basis of PLL, the paper discusses the design of All Digital Phased Locked Loop (ADPLL), including Digital Controlled Oscillator (DCO), Digital Loop Filter (DLF), Frequency Divider (FD), and Phase Detector (PD). The paper mainly focuses on DCO, using the technology of CMOS current logic and MOS varactor, and designs a digital controlled ring oscillator. Besides, DLF is another important part which uses the structure of proportional path and integral path, and is achieved in the paper.As for the design of all digital, ADPLL in the paper only consists of transistors, instead of the passive components such as resistance, capacitance, and inductance, which help save chip area and reduce costs. In the low power consumption, ADPLL makes full use of the technology of frequency control word preset, reducing locked time, which does favor to the reduction of average power consumption of ADPLL.This paper designs a ADPLL-Based Clock Generator using SMIC013technology. Simulation results show that the output frequency range is92—500MHz, the power consumption is0.33mW@92MHz and1.32mW@500MHz, the jitter is42.2ps@92MHz and9.25ps@500MHz. Furthermore, the chip is tested, and the result is much closer to real performance.