Design And Research Of High-Performance And Low-power All Digital Phase-locked Loop

With the rapid development of the integrated circuit industry and the shrinking of the CMOS process size,digital circuits are favored by designers.Phase-Locked Loop(PLL)plays a significant part in modern integrated circuit design and is widely used in various fields,such as RF transceiver systems,wireless sensor network,and high-performance digital circuits.The all-digital phase-locked loop(ADPLL)gradually replaces the traditional analog phase-locked loop with its good portability,high integration and short design cycle.The ADPLL is researched in this article.Time-to-Digital Converter(TDC)and oscillator are the core modules of ADPLL.At the same time,TDC and oscillator are the main source of noise of ADPLL,contributing in-band phase noise and out-of-band phase respectively.Therefore,this article focuses on the research of these two modules,and the specific content is as follows:The proposed TDC structure is based on pipeline with two-level quantization.And a programmable gain time amplifier is proposed,which realizes the programmable gain and can achieve any amplification within the integer range.The TDC sends the quantization error generated in the first stage to the programmable time amplifier for amplification,and then passes through the second stage of quantization.This way improves the accuracy of the TDC,and the resolution is 2ps.The proposed DCO is LC Digitally Controlled Oscillator(DCO).The cross-coupling structure of PMOS and NMOS transistors is used to achieve current multiplexing,which reduces the current of the DCO.This paper proposes a multi-stage capacitance attenuation technology,which improves the resolution of the DCO without??modulator and reduces the power consumption of the DCO.And the unit variable capacitance value is reduced from 3.2f F to 6.7a F.The resolution is 9k Hz.The ADPLL circuit proposed is designed in TSMC 130nm CMOS process.The simulation results show that under the power supply voltage of 1.2V,the circuit power consumption is 5.28m W,the lock time is no more than 2?s,the frequency range is 2.386GHz?2.508GHz,and the phase noise at 1MHz frequency offset is-122.8d Bc/Hz.The chip area is 1.24mm~2.As shown of the DCO's test results,the phase noise at a frequency offset of 1MHz is-126.2700d Bc/Hz and-125.9480d Bc/Hz at2.4GHz and 2.5GHz carrier respectively.