Design Of A Low-Power Counter ASIC And An ATE Test Platform

This thesis research sources and classification of power dissipation in CMOS circuits at first. On that basis, effective tecniques of low-power design are introduced, including low supply voltage/multiple supply voltages design, clock gating, power gating, dynamic voltage and frequency scaling (DVFS). Advantages and disadvantages, as well as applications, of each method are analyzed at the same time.A low-power, high-reliability chip is designed as a Gray Code counter working in industrial rotary encoder system. The methods of multi-level quiescence and clock gating are used, expected to provide a battery life of 5-10 years. The average power consumption of digital circuits is lower than 10μW, with the average current of the chip less than 50μA. Clock calibration and code distance filter are applied to deal with the frequency drift of RC clock and Gray Code instability. Though designed under 0.25μm,2.5V process, the use of dual-edge triggered register, instead of standard DFF(D Flip-Flop), makes the circuit also suitable for 1.8V power supply voltage.At last, an automatic test platform ATE is designed based on FPGA+ARM architecture. The ATE platform is used to apply tests to DUT(device under test), including SPI interface test, RAM test, SNR test and DFT test. The result shows that ATE design has accomplished all of the test processes, satisfying the design requirements.