IC Design Of Second-order Fully Differential Sigma-delta Modulator

Σ-Δ Modulator is the analog part of the Σ-Δ ADC, which is a very important part to determine the performance of the Σ-Δ ADC. Σ-Δ Modulation mode mainly uses the technique of Oversampling and Noise Shaping to decrease the impact of device matching and design complexity on the performance of ADC. It is also applicable to the modern VLSI which has high speed and high integration level. This mode has high precision good linearity low noise strong antijamming capability and easy to integrate with digital circuits. So it becomes the general use in ADC design.This paper designs a second-order fully differential sigma-delta modulator which is used in biomedicine. It is based on technology of CSMC0.5um and the supply voltage of3.3V. We make use of Cadence as well as Matlab to simulate circuit blocks and process data obtained. In the end it is optimized.The design target is using the oversampling ratio of256to get the minimal SNR of100dB and the minimal ENOB of18bits for this second-order fully differential sigma-delta modulator. The input signal bandwidth is2kHz and sample frequency is1.024MHz. The area and power consumption of layout should be optimized. Firstly, in this paper, a comprehensive introduction of the basic theory of Σ-Δ modulator is made. Especially the key point Oversampling and Noise Shaping is given which are the two keys of Σ-Δ Modulation. And it meticulously analyses the performance index of Σ-Δ modulator and determined the performance index for it. Then it analyses the basic structure type of Σ-Δ modulator and the impact of non-ideal factor on it. It also made the related model for them to analyse. Finally it determines the design structure as second-order fully differential sigma-delta modulator structure and use the tool of Cadence to design the schematic and layout for all the circuit modules. It contains fully differential op-amp circuit, bandgap voltage reference circuit, switched-capacitor integrator circuit, high-speed clocked comparator circuit and non-overlapping clock circuit.The result of the design is that the SNR is105.3dB and ENOB is18.09bit. And the area of the layout is1.565mm2. So the design could meet the requirement and the design is successful. It also has theoretical value and practical application in the field of high precision ADC design.