Self Biased Phase Locked Loop Design

With the development of integrated circuits technologies, the speed ofCPU and other SOC solutions increased rapidly, which required higherspeed and higher performance clocks. Further, the high performance clockdesign becomes a challenge today because of low supply voltage and theincreasingly serious variation in deep submicron process. This paperdescribes phase locked loop based on self-biased technique by using anadaptive method and obtain constant loop dynamics which independent withthe multiplication of process, voltage and temperature (PVT).This paper describes a PLL of fixed damping factor ζ and constant loopbandwidth to the operating frequency ratio; explains that self-biased PLL isvirtually independent of PVT variations. According to the analyses of looptransfer function, this paper explains the method of how to choosing the loopparameters. This paper also gives out the differential VCO stage with linearV-f characteristic. Through the theoretically analyses, simulation and siliconfabricated verified the design methodology proposed in this paper.This paper includes the following sections1. The classical phase locked loop modules analysis: including PFDdead zone; charge pump current mismatch effect and clock feedthrough; VCO V-f characteristic and phase noise analyses; thenon-idea effect noise contribution to each block and noise transferfunction analysis. 2. Analyzing the loop transfer function and two important loopparameters: damping factor ζ and loop bandwidth (ωn) to operatingfrequency (ωref) ratio. Using design method to minimize the PVTvariation on the loop stability. Analyzing the basic theory of the selfbiased phase locked loop.3. Expatiating how to design a high performance self-biased phaselocked loop. Solve the problem of getting a stable loop which loopdynamic and parameters independent with PVT variation. Analyzingthe basic theory and the V-I characteristic of symmetric load VCOwhich is the most important module in this PLL with detaileddeduction.4. This chip is fabricated using SMIC55nm low leakage process. Thepower supply is1.2V and the VCO operation range is from0.5GHzto1.5GHz. The silicon area is280um*260um; operation current is4.2mA. The test result shows JRMS=3.8ps, JPK-PK=25ps, respectively.