Research On Broadband Phase-locked Loop Jitter Suppression Technology

As communication standards and data transceiver systems continue to evolve,the requirements for clock generators are increasing.Communication systems require high-precision,low-jitter clock signals,but also need to be able to support different frequency ranges.Therefore,modern clock generators need to have a wider output frequency range and lower output jitter to meet the needs of various applications.Self-biased phase-locked loop can achieve adaptive adjustment of the loop bandwidth,with a wide range of input and output frequencies to meet the requirements of the wide frequency range required for data transceiver systems.However,the self-biased phase-locked loop usually uses a differential structure charge pump in order to realize the voltage self-bias function.When this type of charge pump operates in a wide frequency range,it has a serious current mismatch problem due to the large control voltage variation range of the voltage-controlled oscillator,which leads to the deterioration of the output jitter of the self-biased phase-locked loop.The implementation of a clock generator with a wide frequency range and low jitter using a self-biased structure requires a study of the current mismatch problem in the self-biased phase-locked loop to reduce the output clock jitter of the self-biased phase-locked loop.This paper focuses on the self-biased phase-locked loop jitter suppression technique,and the main research contents are as follows:Ⅰ.In order to realize a phase-locked loop with wide output frequency range and low jitter,a self-biased phase-locked loop with output frequency range of 2～6GHz is designed in this paper using 40 nm CMOS process.When the input reference frequency of the phase-locked loop is 125 MHz and the output frequency is 5GHz,the Jitter P-P is 1.8ps,the overall phase noise is-119.7d Bc/Hz at frequency bias 1MHz,and the Jitter RMS is 893 fs in 10KHz～10MHz.When the output frequency of the phase-locked loop is 2GHz,the Jitter P-P is 31.5 When the phase-locked loop output frequency is 2GHz,the Jitter P-P is 31.5ps;when the phase-locked loop output frequency is 6GHz,the Jitter P-P is 2.3ps.Ⅱ.For the problem of large mismatch current in the charge pump of the self-biased phase lock loop leading to the increase of the phase lock loop output jitter,this paper proposes a digital adaptive mismatch compensation circuit,which amplifies and extracts the locked phase error pulse of the reference clock and the feedback clock,used the error pulse as the control clock of the successive approximation module,and then uses the successive approximation method to adaptively control the size of the compensation current to gradually reduce the phase discrimination error,thereby reducing the output clock signal jitter of the phase-locked loop.When the output frequency of the phase-locked loop is 2GHz,the output jitter is large,and after the current mismatch compensation,the Jitter P-P is reduced to 21.4ps.When the output frequency of the phase-locked loop is4 GHz,the output jitter is still large,but after the current mismatch compensation,the Jitter P-P is reduced to 8.9ps.Simulation results show that the low jitter broadband self-biased phase-locked loop designed in this paper can meet the requirements of SONTE OC-192,PCIE3.0,USB3.2and other communication protocols,and has very high application value.