Research And Design Of Low-Jitter Wide-Tuning Range Charge-Pump Phase-Lock Loops

With advancing VLSI technologies, a System-on-Chip (SoC) can integrate evermore functions, such as the acquisition, conversions, storage, processing, and I/Ointerfacing of signals, on a single chip. The premise of such implementations is reusableIP blocks, which means that various optimized modules can be reused as a unit intodifferent new systems. One of the key components in this design paradigm is the PLL,which can produce variable yet accurate frequency signals from a reference input clock.The output signals can serve as the clock signals for certain digital systems or as the localoscillators for some communication systems.The motivation for this research is to implement a charge-pump PLL, which canprovide a low-jitter, wide-tuning range and small-step programmable clock signal tosupport testing an analog-to-digital converter.The dissertation establishes a complete mathematical analysis based on acontinuous-time approximation. The stability limit of the charge-pump PLL system isanalyzed in detail. Then the behavior simulation is presented. Through this simulation,the circuit parameters are verified.The circuit design is highlighted in the dissertation. Various topologies of eachmodule are introduced and analyzed thoroughly. Comparisons are then made in theirspeed, power consumption, area and stability. A new and improved charge-pump circuit isproposed and the self-biased VCO is optimized. Through these optimizations, weachieved improvements in chip area, power consumption, and phase jitter of this PLL.The prototype is implemented in HUAHONG0.54μm CMOS process. Thesimulation results, demonstrating the improved performance of this charge-pump PLL,are also presented in this dissertation.