Critical Circuit Design Of High-speed Low-power EEPROM Based On0.18μm CMOS Technology

With the advent of the information age, the semiconductor memory has made ansignificant difference in our lives. There is no doubt that it has changed the whole society.As a typical representative of the semiconductor memory, EEPROM plays an importantrole in the small-storage,low-power applications.A8K-bit EEPROM is designed in SMIC0.18μm2P4M CMOS technology with the advantage of low-power consumption，largerange of operating voltage,large memory capacity and high speed operation.First，The paper introduces the research background and research focus of theEEPROM, Then gives the the EEPROM structure and working mechanism. A new type ofmemory cell array is proposed, this cell array keeps both EEPROM’s flexibility ofoperation by byte and flash’s high-speed operation by block.Second, the paper presents the working Principle, optimization and simulation resultsof the EEPROM’s key circuit. It utilises low-power power management scheme forreducing static power consumption and EEPROM read/write operation power consumption.The paper preposes a high voltage generator circuit, significantly reducing the powerconsumption of a boosting after the completion of the EEPROM writing operation. Theoperating clock during boosting the charge pump is also optimized, by offseting the loadcurrent difference in complementary clock, the waveform and synchronization distortionare effectively avoided.Hence, the boosting efficiency are improved and powerconsumption lowered. Through the self-bootstraping design, we eliminate threshold lossesof the sense amplifier input terminal, significantly reducing the sensitive amplifier’s powerconsumption in reading operation, and by adjusting the turning level voltage, we improvethe reliability of the sense amplifier. This article gives the optimization structure oflevel-shifting circuit and design of the limited current, and, then, it significantly reduces thedynamic current consumption of level-shifting circuit. Finally, the simulation and layout of the whole EEPROM is given. The maximumreading speed is8M bit/S, and the maximum writing speed is32K bit/S. The range of theoperation voltage is2~3V. The maximum power consumption current is47.87μA. Theresult shows that the circuit architecture meets the design specifications.