| Since ITU has proposed the concept of―Internet of Things‖——IOT, it has beenreceived broadly acception by almost all countries in the world. It has been raised to astrategic height of the development of the nation’s economy and technology. Perceivedas a crucial basic component of the IOT, the Radio Frequency Identification——RFIDperforms as the entrance for the subjects needed to be connected to the IOT. As a result,RFID becomes one of the most important key points among other core technologies ofIOT. Among varied classification of RFID, the passive RFID works in Ultra HighFrequency——UHF band is the most important research hot point, as it has a farenough read rang and other valuable merits.Taking the above background into consideration, the related key design techniquesof the passive UHF RFID have been researched in this paper, based on thesummarization of the existing low power design techniques. The research productionsare finally formed as a complete UHF RFID tag chip, which has been taped out andtested. The detail research contents of this paper include:Firstly, a subthreshold RF/Analog frontend is proposed in this paper, the power ofwhich is optimized by a global energy management at the systematic level. Moreover,the detail circuits design of the RF/Analog frontend have been researched in this paper.The most efforts are laid on the research of the design of reference circuit and clockgenerator. Where: a subthreshold referecnce with the merits of low power, highprecision and small chip size is proposed. To compensate the substrate bias effect ofMOS transistor, which will deteriorate the precision of the reference, a―pseuod diode‖is introduced; the proposed calibreation solution for the clock generator can effectivelyreduce the calibreation cost, which helps the realization of the real-time, fieldcalibration of the clock frequency. Test results show that, the working current of theproposed RF/Analog frontend based on the above design techniques is3.6μA, which issmall enough for UHF RFID application.Secondly, low power non-volatile memory (NVM) has become the crucial restraintof the practical application of the RFID, and comparatively, the related research isrelatively insufficient. Thus, in the consideration of the process cost and maturity,EEPROM is adopted as the memory for RFID, and the related design techniques aimedat low-power and high-reliability is researched in this paper. Where: to optimize thepower of the read circuit, a new pre-charge-adaptive data detect scheme is proposed. Itcuts the DC path from the power source to the ground. Thus, the read power of the EEPROM is greatly reduced. To improve the anti-read-error ability, a global timesequence control of the read operation and a feedback scheme are introduced, whichendow the read circuit with the merit of process parameter adaptivity. As a result, thereliability of the read circuit is effectively improved; What is more, a time-devided highvoltage charge pump with low power-up current surge is proposed in this paper. Withthe help of a reasonable time sequence control, the proposed charge pump ispowered-up in a pipeline way. Finally, without increacing the power and the cost, andwithout sacrificing the pump efficiency and driving ability, the large current surge at thepower-up phase is effectively reduced.Based on the above design techniques, a complete EEPROM IP is designed andtaped out. The test results of the EEPROM IP show that the read and write current of theEEPROM are1.18μA and33μA respectively. The successful verfication of the proposedEEPROM IP also has the same practical significance to solve the design difficulties ofthe portable general memory.Finally, together with the developed digital baseband, the proposed RF/Analogfrontend and the EEPROM IP form a full RFID tag chip. The tag chip was finallytaped out and successfully tested through a commercial reader, the read rang is atleaset6m, and the write rang is1.8m. |
PDF Full Text Request