Research And Design Of 2K High-speed Low-power EEPROM

With the development of information industry, semiconductor memory plays a decisive role in people’s work, study and daily life, even affect the development of changes in society as a whole industry. As a typical representative of small capacity, low power consumption semiconductor memory, Electrically Erasable Programmable Read Only Memory has been widely used.In this thesis, we design a 2Kb serial EEPROM with SMIC 0.18 um 2P4M CMOS process. The memory has advantages of high speed, low power consumption and wide voltage range. In order to achieve the fast read of inside data, we listed multiple designs scheme for the sense amplifier and to use the best one. To reduce the consumption, we directly adopted the power supply instead of LDO or DC-DC circuits for voltage conversion in the chip, and take some measures to the whole structure design and current control of the important modules. Establish standard cell libraries of 3V~5.5V range in order to implement all modules in the circuit can work at 3V~5.5V voltage. Thesis conducts in-depth research of EEPROM’s internal analog part(including: a storage unit, reference, high voltage generation circuit, the sense amplifier). After the simulation of separate functional modules and each part meets the design requirements, we did overall function emulation of EEPROM, including program, erase and readout. After the completion of layout drawing, we extracted the parasitic effect from the layout and did the after simulation, the result is closer to the practical application of the circuit parameters. Under 25 ℃, the power supply voltage of 3V, the reference output voltage is 1.26 V, the generated high voltage is 15.6V. Static current at 5.5V 125 ℃, the maximum value is 28 u A, meet the design requirements. After the tapeout, we will do the function test for the product.