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Research Of PCGC Codes Algorithms And FPGA Implementation

Posted on:2014-09-17Degree:MasterType:Thesis
Country:ChinaCandidate:C S ZhangFull Text:PDF
GTID:2268330422457516Subject:Communication and Information System
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This dissertation research the FPGA implementation of the QC-LDPC encodingand decoding algorithm, the detailed design is given for every step in the algorithm,including the structure of check matrix, storage way, the flexibility concerning designof code length and rate. Firstly, several classical algorithms are analyzed in errorcorrection performance and computation complexity, the appropriate algorithm isselected as a design goal. Secondly, each module is designed step by step according tothe selected algorithm. Finally, simulation results and analysis are given.The paper can be divided into three parts:In the first part, LDPC code encoding algorithms and RU coding algorithm areintroduced. The check matrix of1/2code rate is selected in IEEE802.16e standard forFPGA design and implementation of QC-LDPC code. A kind of FPGA encodingmodule is designed with controlled extension factor and substituted check matrix, ithas a strong portability. The simulation results and resource consumption for analysisand verification are given in the end.In the second part, we research the two types of LDPC codes decodingalgorithms, i.e. hard decision algorithm and soft decision algorithm: WBF algorithmand the min-sum algorithm. WBF algorithm of FPGA design is one of modules withcontrolled extension factor and substituted check matrix. Min-sum algorithm usesserial structure to design and implementation. The simulation results and resourceconsumption for analysis and verification are given in the end.In the third part, focusing on the LDPC code decoding convergence speed anderror floor, we research the structural features of parallel concatenated PCGC codesdecoding and design a cascade parallel decoding structure which is called as DWBF.The simulation results and resource consumption for analysis and verification aregiven in the end.The aim of this study is to make the LDPC code application in the actual systemmore simple, more efficient and more feasible. The result of this study can providecertain reference for future research of LDPC codes.
Keywords/Search Tags:QC-LDPC, RU coding algorithm, WBF algorithm, Min. sum algorithm, DWBF algorithm, FPGA implementation
PDF Full Text Request
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