The Research And Fpga Implementation Of Ldpc Coding And Decoding Techniques In Sc-Fde Communication System

As the development of communication technique requires more about the speed and quality of communication system, SC-FDE system gains more and more attention in recent years with the advantages of anti-multipath interference ability and lower hardware complexity. In this paper, the implementation of SC-FDE communication system and the LDPC encoding and decoding techniques have been studied and accomplished. Comparing several equation algorithm and channel estimate algorithm, this paper chooses ZF algorithm as the hardware implantation method with its low hardware complexity. The FPGA designs of several important modules and the performance simulation in SUI-3channel model have been given out in this paper.The LDPC code with1/2rate and extension factor value64in IEEE802.16e is chosen in this paper for the LDPC techniques. For the encoding part, the encoding algorithm equations are deduced based on the base check matrix and its complexity analysis is provided; for the decoding part, this paper compares a variety of LDPC decoding algorithms and chooses minimum-sum algorithm which is easy to realize in hardware as the implementation scheme.The implementation processes of FPGA design for encoding and decoding systems are studied respectively for the hardware realization of LDPC system. In order to exploit the parallel advantage of FPGA, this paper applies full parallel structure to achieve LDPC fast-encoding system; according to the analysis of LDPC decoding equations, a LDPC decoding system with double-packages decoding has been designed and also a pipeline improvement is applied to some key units of VUC and HUC which increases decoding speed. Finally, this paper tests the whole system of LDPC and proves it can work normally.