The Encoding And Decoding Research And Hardware Implementation Of LDPC Codes Based On FPGA

As the development of information technology becoming faster and faster,the requirements for information transmission are becoming increasingly stringent.As a result of the great error probability caused by high transmission efficiency,it is required to choose a codec technology with good error correcting performance in the process of mobile communication.In this paper,low density parity check(LDPC)code with close performance to Shannon limit is chosen as the error-correcting code to realize the self-sent and self-received communication system under quadrature phase shift keyin(QPSK)modulation mode.LDPC code shows its good performance in decoding when they are in medium or long code conditions.Has been widely used in DVB-S2,4G communication systems and satellite communications,and has become a 5G medium or long code coding scheme.Firstly,this paper introduced the development and application status of LDPC code,and focused on the LDPC coding and decoding algorithm.For the encoding algorithms,according to the complexity of hardware implementation,this paper chooses the easy-to-implement QC(quasi-cyclic)LDPC coding algorithm.Check matrix's sub-matrix had cyclic characteristics in QC-LDPC coding algorithm,so QC-LDPC coding algorithm need low storage and computation.For the decoding algorithms,we first introduce the BP(Belief Propagation)algorithm and its improved LLR(Log Likelihood Ratio)BP decoding algorithm.The two algorithms performs well in decoding process but are not conducive to hardware implementation.Then this paper focus on the min-sum decoding algorithm and the two inproved algorithms of it——the normalized BP-based algorithm and the offset BP-based algorithm.Finally,this paper simulates the LDPC code decoding algorithm,code length,bit rate,and iteration numbers and other parameters by using the Matlab software.According to the influence of each parameter on the bit error rate performance of the system,the normalized min-sum decoding algorithm is chosed to implement the decoding.Then,according to the determined parameters,the design of LDPC code codec is realized in FPGA.At the same time,in order to realize the complete communication system,this paper designs and implements QPSK modulation and demodulation system in FPGA.Then,using modusim software to simulate the realization process of the module,it proves the correctness of the algorithm.Finally,this paper introduces the software defined radio(SDR)platform developed by the laboratory,and uses the platform to test the whole communication system.By implementing the spontaneous self-received function of QPSK modulation and demodulation signal under LDPC coding and decoding,the bit error rate is calculated under different signal-to-noise ratio.It is proved that the decoding performance meets the requirements of the index.And this verifies the correctness of the system.