The Research And FPGA Realization Of LDPC In DMB-TH System

As is known to all, error correcting code was used in communication system to improve the reliability and power utilization of channel transmission. Low density parity-check codes (LDPC code), a kind of error correcting code, was invented by Robert Gallager in 1962. Given the development condition of computer technology at that time, the complexity of LDPC hardware realization was out of the question, so the classical model of LDPC, in other words regular LDPC, was largely forgotten. Until 1995, it finally came back to the field of research and became the focus. It has been shown that LDPC can perform very close to the Shannon capacity limit. LDPC has a significantly lower complexity than Turbo codes at the code lengths, performance and S/N. Besides, LDPC decoder is suitable for fully parallel implementation. This has significant advantages when considering long codes. It is safe to say that LDPC surely has a more promising future. The truth is LDPC has been adopted at so many research achievements currently: such as Wireless LAN IEEE 802.11, Terrestrial Broadcasting Transmitting system DVB-S2 and China Mobile Multimedia Broadcast (CMMB). In China Terrestrial DTV Standard (GB20600-2006) which was released recently, the channel coding scheme of it's multi-carrier system (DMB-TH) also use LDPC.This paper mainly focuses on the research and analysis of the CODEC algorithm and the performance of LDPC used in DMB-TH system. In addition, a coder of the DMB-TH system is realized with FPGA.In order to make it easy to understand, the first chapter of this paper gives the introduction of LDPC code. The second chapter will talk about the principle of LDPC code, including the developing history, definition, analysis of Tanner graph, random construction method, arithmetic construction method, classical decode scheme and contemporary decode scheme. Based on what we introduced above, the third chapter will talk about the characteristic of a very special kind of LDPC code, named QC-LDPC code (quasi-cyclic LDPC code). Further, this paper gives the parameters and the construction method of the QC-LDPC used in DMB-TH system. From the fourth chapter on, we move into the realization of the LDPC code. The CODEC algorithm of QCLDPC which is suitable for hardware realization is concluded. Additionally, Matlab is used to conduct the performance simulation of the LDPC code used in DMB-TH system, and the simulation result proves that the code's performance is pretty good. In the last chapter, I will talk about the design idea and FPGA design structure of the LDPC coder for DMB-TH system which can support QPSK, 16QAM and 64QAM modulation modes. The validity of this coder will be demonstrated by the timing simulation result.