Dvb - T2 System Research And The Fpga Implementation Of Ldpc Code Coding Algorithm

Channel coding is a key technology for baseband signal processing in digital communication systems. A common digital communication frame work first established by C. Shannon in his1948seminal paper, A Mathematical Theory of Communication. Shannon showed that codes exist that provide arbitrarily reliable communication. The channel coding theorem lays a theoretical foundation for the development of channel coding.The main purpose of this paper is to research and implement the LDPC encoder in DVB-T2communication system. A LDPC code is a linear block code given by the null space of a parity-check matrix H that has a low density of Is, and LDPC codes performance is very close to the Shannon limit. LDPC codes in digital communication systems are widely used and have good prospects for development. This paper mainly discusses the LDPC codes characteristics and implementation in the DVB-T2system from the following aspects:First of all, this paper introduces the basic concepts and principles of the channel coding. As the theoretical basis including professional knowledges of the channel capacity, channel coding theorem, and the definition of the linear block code of the follow-up.Secondly, described in detail the basic concepts, features, and encoding and decoding algorithms of LDPC codes. There are a variety of LDPC code parity check matrix construction methods. To construct LDPC codes with good error correction performance, you must meet three conditions:no short loop, no low weight codewords, and the minimum of code spacing as large as possible.Third, analysised the encoding algorithm of LDPC codes in detail in the DVB-T2system. The LDPC codes are a type of IRA codes which parity check matrix that is semi-random cycle has dual diagonal structure. This paper designed a parallel encoding algorithm and finished performance simulation for the encoding algorithm.Fourth, elaborated the design of the LDPC encoder on FPGA. The key technologies to implement LDPC encoder including the data path design of iterative accumulation of the barrel shifter ouputs and the control path design of all the code rates compatible. The LDPC encoder has high throughput characteristic.Finally, this paper designed the verification method for the LDPC encoder. The verification module mainly includes two sub-modules which are signal generatoin sub-module and codeword read sub-module. Codeword read sub-module returns the LDPC encoder’s output to the host computer to determine the correctness of the code-word through the UART.This paper researched the LDPC encoding algorithm in DVB-T2system and implemented the LDPC encoder on FPGA. In the worst case, short frame and5/6code rate, BER has to reach10-7while SNR is about3.2dB. The throughtput of the LDPC encoder could be achieved1OGbps.