A Kind Of Effective Qc Ldpc Design And Decoder Fpga Implementation

Along with the development of the communication technology, higherrequirement for the quality of the communication was put forward by people.Gallager proposed Low density parity-check (LDPC) code in1962. Because of its lowcomplexity of decoding and lower error floor, it has become a moderncommunication application hot spot. Quasi-cyclic LDPC is an important subclass ofLDPC codes. It has many advantages,what other structures have not. Therefore, it hasbecome the first choice in many communication standard error correction scheme.First，The article put forward a kind of QC-LDPC code of half decision structure.This kind of half decided approximate lower triangular structure can improve theQC-LDPC code design flexibility,and can provide the lowly error probability thandouble diagonal structure.It was than made comparition between this structure ofQC-LDPC code and the code in IEEE802.16e. Although the row weights in the orderof code A is different from IEEE802.16e, the distribution of the row weights in twocodes are the same.This paper carried on the detailed in-depth research to the structure of theQC-LDPC code in theoretically,and made the software simulation designation ofField Programmable gates array (Field Programmable Gates Array, FPGA) to it inhard practically.In the aspect of theory, through comparing various coding algorithms, and putsforward the fast coding algorithm of this QC-LDPC code.In addition, compared withBP algorithm, offset BP-Based algorithm has smaller computational complexity andcan get the performance near the BP algorithm, as long as the normalized factor ofwhose select appropriate. So in this article, the offset BP-Based decoding algorithmwas adopted. Finally, make up the simulation to encoding and decoding algorithmsthrough the matlab.In the hardware, chosed the structure of hardware realization of two algorithmsamong encoding and decoding algorithms,what was the structure of part the parallel.In QuartusII8.0software platform, it gave respectively encoder and decoder FPGAmethod,through the Verilog HDL hardware description language,with ModelSimsimulation tools. It included general structure design, the design of each child module, and gave the function simulation and the results after Analysis and synthesis andplace Route.