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Modeling And Simulation For Multi-topologies Reconfigurable Network On-chip

Posted on:2013-09-23Degree:MasterType:Thesis
Country:ChinaCandidate:Y ZhouFull Text:PDF
GTID:2268330422452888Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Network-on-Chip(NoC) is an advanced solution to solve the complex problems onSystem-on-chip(SoC), and become the inevitable trend of the SoC. With different design, the NoCcomponents such as topology, routing algorithm, basic component design, etc, have great differencesin the performance, and because of that, building a general platform of reconfigurable NoC systemmodeling become particularly important.The paper proposes the design and modeling process of reconfigurable NoC system byresearching the architecture of NoC and analyzing the reconfigurable characteristics of basiccomponents of NoC. By the reconfigurable analysis of the structural properties of NoC, such astopology, routing algorithms and buffer depth, etc., the paper specifies the properties into differentparameters of NoC system. Based on these parameters, the paper designs components to support themodeling, which include topology connection module, routing module and network adaptermodule.Making use of these reconfigurable components, together with reconfigurable configurationsoftware, the paper realizes the modeling of NoC system with high speed and flexibility. With the useof simulator-Modelsim, the paper analyzes the performances of RTL model of NoC system to verifythe effectiveness of the platform modeling. Also, the paper highlights the performances of throughputand latency.On the basis of adequate research and analysis of2DMesh, Torus and FT, the paper putsforwards a two-layer extendable network topology, GP-Ring. Also, the topology overcomes the defectof too long diameter in2DMesh network and combines the advantages of general Petersen, such assymmetry, strong orthogonality and simple design. With the considerations of the features of GP-Ring,the deadlock-free routing algorithms of GP-Ring is presented and implemented. Indeed, thealgorithms can select the output port of news according to the relative coordinates of routing node andtarget node in GP-Ring network.The platform implemented in the paper is suitable for multiple topology, which is quite helpfulfor shortening the cost of establishing the NoC system. For the design of NoC system with differentapplication requirement, the platform possesses favorable commonality.
Keywords/Search Tags:Network on-Chip, Reconfigurable Network on-Chip, Topology, Performance Evaluation
PDF Full Text Request
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