Performance Evaluation For Various Network-on-Chip Topologies

With the increasing complexity of SoC, especially the emergence of MPSoC, on-chip communication has became the performance bottleneck of SoC. Efficient on-chip communication architecture has a huge impact on the performance of system. In recent years, people have proposed a new on-chip communication architecture - . Network-on-Chip. Compared with traditional architectures, on-chip network's scalability and capability of full use of processor's parallel processing improve the performance of SoC.Network-on-Chip has different topologies, such as 2D Mesh, Torus, ring, hybrid, etc. In order to find the conformable and optimal performance topological structure for practical application, we need a criterion of performance evaluation system.This paper has built a Network-on-Chip performance evaluation platform with variable number of nodes, and evaluates a new ring structure and traditional 2D Mesh topology. By adopting the virtual output queue technology, the new ring topology NoC architecture completely resolves head of line blocking and deadlock which exist in traditional ring topology architecture. By changing ring number, flit sending speed and Buff depth, we evaluate the performance of this system in the experiment. Finally we get two conclusions: 1) When the number of node is fixed at 16 for the new ring topology NoC architecture, the performance of bidirectional ring topology whose buff depth is 2-4 flits is better and is suitable for practical application; 2) When the node number is less than 9, the performance of new bidirectional ring topology architecture is better than traditional 2D Mesh topology, when the number of nodes is greater than 9, the performance of new bidirectional ring topology architecture begins to decline, especially in the case of high flit sending speed the performance is not as good as 2D Mesh.