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Research On A Dynamical Reconfigurable Router Based Network-on-Chip Architecture

Posted on:2013-05-17Degree:MasterType:Thesis
Country:ChinaCandidate:F Y LiuFull Text:PDF
GTID:2248330395956765Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Network-on-Chip (NoC) is an important technology for the communication framework of large-scale Multi-Processor System-on-Chip (MPSoC), in which on-chip router is the kernel component. Router architecture and control mechanisms are crucial for the communication efficiency and power cost of NoC. Traditional static-configured routers have the disadvantages of poor flexibility and scalability, so the application properties of MPSoC will not be satisfied using these routers. Dynamical-configured routers can adapt their operating mode in accordance with the network state variation, thus the flexibility and scalability of the system will be improved. These dynamical-configured routers can significantly reduce the development time of NoC. This paper researches on the on-chip router architecture and its control mechanisms. And DCRouter, a dynamical-configured router, is proposed. Then, DCRouter is applied to the EMesh topology, in which the IP cores and routers are connected in a multiple-to-multiple way, to construct the dynamical-configured NoC, DCNoC.The main contributions of this paper include:(1) Current research results on NoC design theory and some commercial products are concluded, especially the significance of dynamical configured NoC architecture.(2) Basic router architecture and its control mechanisms are researched in details, including the basic structure and principles of wormhole router and virtual-channel router, adaptive deadlock-free routing algorithms, etc.(3) A NoC thermal model is proposed, and then a dynamical thermal-balance routing algorithm, DTBR, is designed. DTBR algorithm can achieve much better performance in aspects of delay, throughput, and thermal distribution according to the simulation results.(4) An improved Noxim simulator is designed, which is based on virtual-channel router, and can be used to simulate the packet delay and throughput performance of NoC in different parameters.(5) Topologies of multi-to-multi connection between IP cores and routers are analyzed, and a dynamical-configured NoC, DCNoC, is proposed. DCNoC is based on the EMesh topology, in which the IP core can dynamically access the on-chip router.(6) Based on the research results of on-chip router architecture and control mechanisms, as well as the dynamical-configured properties of DCNoC, the DCRouter is designed. In DCRouter the number of accessing channels between IP core and router, and the way they are connected can be configured.(7) Finally, we develop a system-level performance simulator for DCNoC. The delay and throughput performance is analyzed using the simulation results. Moreover, with the help of Xilinx ISE12.1, synthesized hardware circuits and behavioral simulation of different configured DCNoCs are achieved.
Keywords/Search Tags:Network-on-Chip, Reconfigurable Router, Adaptive Routing Algorithm, Performance Evaluation, Circuits Design
PDF Full Text Request
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