Study On Topology And Fault Tolerant Scheme Of3-D Network On Chip

As an effective solution to the complex SoC interconnects, Network on Chip (NoC) is receivingattention by academic circles for low delay, high bandwidth and flexibility. The conventional2D NoChas limited floorplanning choices, and consequently, it limits the performance enhancements arisingout of NoC architectures.3D NoC is capable of achieving better performance, functionality, andpackaging density compared to2D NoCs. In the many aspects of3D-NoC design, it is very importantthat selecting appropriate topology to improve the network performance. In addition, with theincreasing scale of3D-NoC design, the probability of system failure is also corresponding increase.Hence the fault tolerance scheme for3D-NoC is an important means to ensure the reliability of3D-NoC communication. This thesis focus on the3D-NoC topology and fault-tolerant scheme, andtries to solve3D-NoC evaluation methods, regular and irregular3D topology design, permanent faultsand transient fault tolerant scheme.The thesis firstly studied the evaluation methods of latency and power consumption in3D-NoC,and established a set of theoretical calculated model for3D-NoC latency and power consumption,then selected the most popular3D topologies for analysis. On the basis of analyzing the influence oftopology features over the performance by the theoretical analysis and software simulation, theperformance of four topologies in throughput, latency and power consumption were tested andcompared. The results provides the reference for the optimization of3D topology design, alsoestablish the basis of the evaluation for the following research.A regular3D topology generation method called3D-Spidergon is proposed. Aiming atestablishing relationships between the topology architecture and the latency, the3D topology latencymodel based on prototype is proposed, and then the optimization topology structure with minimumlatency is determined based on it. In accordance with the structure, we design adaptive routingalgorithm, which sets longitudinal direction priority to search the equivalent minimum path adaptivelybetween the source nodes and the destination nodes, in order to increase network throughput. Thesimulation shows that in case of approximate saturation network, compared with the same scale3Dmesh structure,3D-Spidergon enjoys17%less latency, and16.7%more network throughput.In order to take advantage of short inter-layer interconnects in vertical for3D-NoC, a novelhybrid3D NoC-Bus architecture is proposed. For vertical link, a Fake Token Bus architecture iselaborated, which utilizes the bandwidth efficiently by updating token synchronously. Based on thisbus architecture, a methodology of hybrid3D NoC-Bus design is introduced. The network hybridizes with the bus in vertical link and distributes long links of the full connected network into differentlayers, which achieves a network with a diameter of only3hops and limited radix. In addition, acongestion-aware routing algorithm applied to the hybrid network is proposed. Experimental resultsshow that, under uniform random traffic, our network can achieve a34.4%and13.1%reduction inlatency and a43%and7%reduction in power consumption compared to the3D-Mesh and long-linkstopology. While under hotspot traffic, our network can achieve a36.9%and13.3%reduction inlatency and a48%and5%reduction in power consumption.To tolerant the permanent fault occurred in the3D-NoC, A fault-tolerant and deadlock-freerouting algorithm DPRA which applied in3D-Mesh is proposed. Aiming at the absence of fault modein3D topology, a new definition of fault block is proposed to reduce the region of fault and theaffected healthy node, and then a detour-path construction algorithm is designed to implement theconstruction of fault block and the generation of detour-path list by recursive of message deliver. Thedetour-path routing algorithm combines the detour-path list and routing rules, make a detour to avoidthe fault block by adding detour-path list into the header flit. The experimental results show that thealgorithm achieves9.7%,10.3%,13.3%,13.1%,13.4%reduction in latency and17.8%,19.6%,15.6%,9.6%,10.2%reduction in power consumption respectively compared to the forbidden turnmode routing, in the node failure rate of2%,4%,6%,8%and10%.Aiming at the crosstalk which leads to transient faults, a joint coding scheme CAJC combinedwith crosstalk avoidance code, low power code and error control code is proposed. To guarantee thecrosstalk avoidance, a crosstalk avoidance code based on Fibonacci numeral system is applied, whichreduce the influence of crosstalk over the data transfer correct rate. The low power code reduce thereversal rate of interconnects, which reduces the power consummation. And the error control codeachieved error detection by adding parity bits. Based on the joint code, the schemes of codec applyingto fault-tolerant router are analyzed and "once encode, multiple decode" scheme is chosen as thedesign method of fault tolerant router. The experimental result shows that the proposed joint codescheme can achieve the crosstalk avoidance and decrease of delay and power by the lower areaoverhead.