Study On Reconfigurable Heterogenous Multi Processor System On Chip

Multi-processor system on chip (MPSoC), which has integrated a large number of general-purpose processor, DSP, ASIP and other IP cores, to satisfy the various demands of applications. Meanwhile, growing with the diversity of modern embedded applications, it's required to customize hardware computing platform towards various situations. Reconfigurable MPSoCas proposed a solution which combines traditional general-purpose microprocessor with space-based parallel computing; therefore can be ultilized within the hardware reconfigurable programmable logic devices, to adapt its characteristics for different applications to customize execution environment, enabling full use of diverse on-chip computing resources more effectively to meet the requirements of different applications.However, the reconfiguration of hardware system needs the the hardware redesign and implementation, which makes great difference between traditional multi processor designs. The dynamic modification poses a significant challenge in MPSoC designs, including the runtime task partition and scheduling, interconnection and communication mechanism, programming patterns, to explore the parallelism and exploit the system performance.To address the problems above, the dissertation focuses on the key technogies of reconfigurable heterogenous MPSoC system. The main contributions are listed as follows:1. Builds a research environment for reconfigurable heterogenous MPSoC (1) Designs and implements an ADL based MPSoC simulator, to evaluate the MPSoC system solutions.(2) Constructs a basic research platform based on Xilinx FPGA. The platform integrates diverse general purpose processor and several heterogenous IP cores, which can be used to verify the concepts of task partition, scheduling and interconnection.2. Presents a reconfigurable heterogenous MPSoC system architecture. By introducing SOA concept and service-execution flow model, we present a FPGA-based service-oriented hierarchical model. The model builds serval kinds of servants on the computing resources, including scheduling servant, application servant, software and hardware computing servant. Scheduling servant is incharge of task partition and scheduling, the application servants provides programming interfaces to users, while computing servants mainly run the tasks. The introduction of SOA enhances the scalability of the system, and also can provide unified interfaces to users, which can help to solve the"programming wall"problem.3. Studies on the SW/HW dynamic reconfiguration and task scheduling.(1) First applies dynamical profiling technology to locate the hospot of an application, and then propose a performance evaluation method with dynamic HW/SW partitioning and scheduling. The method can be used to guide the hardware platform configuration for different levels of the real-time systems requirements.(2) Presents a task scheduling algorithm MP-Tomasulo for MPSoC. The algorithm utilizes instruction set scheduling algorithm to accomplish task level parallelism. It can automatically eliminate data dependence between tasks (WAW and WAR), and therefore largely increase the performances.4. Proposes on-chip interconnect model and communication mechanism(1) Implements a peer to peer bus based star network and related communication model. The architecture has been demonstrated for effective communication with low hardware cost, can be reconfigured statically to make it easier to construct a prototype system.(2) Applies crossbar based reconfigurable interconnection to MPSoC and high speed SSD design, and also implements a prototype systems respectively. The mechanism can reconfigure the data path at run-tim, and therefore can obtain more flexibility.