Research On Construction Of Network Topology And On-Chip Router For Network On Chip (NOC)

Rapid development of integrated circuit brings chip design into billion-transistor field. It will allow more modules be integrated on a single chip. As the number of cores on a systematic chip increased, traditional SOC design methodology based on on-chip bus will not fit the requirements for multi-core system's communication. Therefore, a new multi-core on-chip interconnection structure——Network on Chip(NOC) become a hot point of research. NOC provides effective, reliable and flexible infrastructures for system modules, and it is becoming one of the most potential solutions for on-chip system intra-communication. This thesis researches and designs the network topology and on-chip router of the NOC system.Based on analysis of the related research and basic knowledge and important technologies, this thesis uses a hybrid network with BUS structure as the research direction of the NOC network topology. And the wormhole switching mechanism and virtual channel technology are selected as the design ideas for the on-chip router.The network topology automatic synthesis algorithm is proposed in this paper. The area overhead is chosen to be the objective function for the algorithm. The algorithm use the minimum rectilinear Steiner tree as the basic structure of the network, and use the department algorithm for group the communication tasks to generate the actual network topology. Finally, some communication tasks with delay constraints are connected to the BUS which is inserted into the network. We use C++ to implement the algorithm program which can generate the network topology automatically. Through the analysis for the examples and comparison to other structures, we prove that the topology generated by the algorithm can reduce the area overhead and transmission delay effectively.In this paper, a on-chip router is designed by using the verilog language. According to the function and application, the router is divided into five functional modules. Each sub-module and the whole router are simulated and validated.