Design Of CMOS Time Interleaved ADC System Based On Background Calibration

Pipeline analog-to-digital converter(ADC)is a popular Nyquist rate data converter because of its ability to maintain high accuracy at high conversion rates.With the rapid development of applications such as audio video,instrumentation,and high-speed data acquisition,pipelined ADC design is moving towards higher speed,higher accuracy,lower supply voltage and power consumption.The purpose of this subject is to realize the overall system modeling,circuit design,algorithm design and hardware implementation of a time interleaved Pipeline ADC based on background calibration algorithm.In this thesis,Cadence Virtuoso software is used to design a 12-bit high speed fully differential Pipeline ADC based on 180 nm CMOS technology.At the same time,double sampling rate is realized by a structure of two channels time interleaved together.ADC differential input voltage range is 200 mV?800m V,power supply voltage is 1.8 V.The pipeline ADC consists of ten 1.5-bit sub stages and one 2-bit Flash ADC.The overall ADC structure also consists of a series of digital calibration circuits.In this thesis,a high-speed low onresistance bootstrap switch is proposed,with an on-resistance of about 36.76% of the existing bootstrap switch,the output effective bit count is improved by 1.39 bit to improve the bootstrap switch performance.The overall ADC circuit meets the design requirements.The time interleaving model of the Pipeline ADC is built in Matlab Simulink simulation software.A dual-channel Split ADC background calibration algorithm based on PN dithering is proposed,which can eliminate the gain error,capacitance mismatch and nonlinearity of the Pipeline ADC through separable two-stage calibration.The first-stage PN dithering calibration is implemented through the FPGA Xilinx development board hardware,and the second-stage Split ADC calibration is implemented through Matlab code.The problem that the Split ADC algorithm cannot converge in the presence of a large number of errors and the large calibration period required for PN dithering calibration is solved.A 5% gain error and a 2% capacitance mismatch are introduced into the first five substages of the ADC in the time interleaving model.The simulation result after background calibration shows that when the sampling rate is 100 MHz,the effective number bits of ADC after calibrtion is 11.23 bit,which is 5.14 bit higher than that before calibration.The SFDR is84.853 dB,40.344 dB higher than before calibration,verifying the effectiveness of the designed algorithm.