Research On Low Power Deterministic BIST Based On Genetic Algorithm-Folding Counter

With the development of integrated circuit, manufacturing costs and time-before-market of chips have been reduced. However, for chips, difficulties of test haven't been reduced until the advent of DFT technology even BIST technology. Simultaneously, low-power-dissipation test has become one of the goals of development. Dissipation during test is mainly due to supply voltage, clock frequency and jumps in circuit. If supply voltage or clock frequency is reduced, time for test will be increased, and a number of faults which only appears in high-frequency test will be detected difficultly. Reducing jumps is therefore the best way to low-power-dissipation test.Current research for low power BIST includes low-power ATPG technology, improving structure of scan chains, designing scan unit and circuit division technology. Research in Low-power ATPG technology is the main work in this dissertation. For power dissipation of deterministic BIST, optimization algorithm and store-and-generate technology have been researched. In order to reduce power dissipation during test, optimization algorithm for vector sequence and circuit for ATPG have been improved. In the choice among optimization strategies, probabilistic search technology in Genetic Algorithm is more conducive to optimizing overall situation, so Genetic Algorithm is used to optimize vector sequence. Based on current Genetic Algorithm for only reducing jumps in circuit-under-test, jumps in circuit for ATPG is considered. Double-objective Genetic Algorithm is designed for reducing jumps both from circuit-under-test and ATPG circuit. According to actual computing, decimal integer code equivalent to vector is designed, as well as double-objective fitness function, corresponding probability for selection, mutation and cross. On the other hand, Folding Counter method has been used in ATPG circuit. Current Folding Counter method has been changed to improve relevance between adjacent vectors. Optimized vectors are un-reseed in ATPG circuit to reduce jumps from both circuit-under-test and ATPG circuit as far as possible. Finally, experiments on bench mark circuits and comparison with current research results confirmed the validity of the methods in this dissertation.