Research On Multi-channel Time-interleaved High Speed Sampling Algorithm And FPGA Design

Analog to Digital Converter(ADC)is widely applied in computer,communication and military fields.With the continuous development of digital signal processing technology,the sampling rate and sampling precision of ADC are required higher in various fields.With the traditional single-channel ADC process technology becoming bottleneck and the sampling rate is difficult to be improved,the multi-channel time interleaved ADC uses multiple chip and parallel alternating sampling architecture to improve the sampling rate.However,the actual production of the chip can not be exactly the same and the sampling clock accurary is difficult to achieve,there are mismatch errors between channels,resulting in significant performance such as ENOB(Effective Number Of Bits)reducing a lot.In order to maximize the use of time-interleaved sampling structure,it is urgent to estimate and correct the error.According to the above structure and problems,the following work is done in this paper:(1)The time-interleaved sampling technique is studied from the aspect of system structure,workflow and sampling timing.The spurious location caused by the three main mismatch errors,such as offset error,gain error and time error,is theoretically derived,and the results are verified by simulation.The relationship between the signal to noise and distortion ratio(SNDR)of ADC performance index and the three errors is emphatically studied,and the impact of the errors on the SNDR is analyzed by the specific numerical analysis.(2)According to the correction order of bias error,gain error and time error,combined with the existing correction technology,the corresponding digital domain correction mode is put forward,and the simulation model is established based on this method.Simulation results show the suripus could be suppressed effectively and sampling performance could be improved a lot by the selected method.Considering algorithm hardware implementation complexity and existing technical conditions,a combination of software and hardware is proposed,with error estimation by host computer and error correction by FPGA,so as to achieve a blind equalization correction algorithm with high correction accuracy.(3)The four channel TI-ADC sampling board is debugged to achieve the high sampling rate of 5Gsps and the resolution of 10 bit.The VC707 development board is used to correct the sampling data of the ADC card.The design process of the processing scheme is described in terms of overall scheme,device selection,transmission interface,data cache and digital domain of correction algorithm.The test results indicate that for single-frequency signal,the ENOB of samples can reach 7.5 bit.For linear frequency modulation,the broadband spurs can be suppressed effectively.