High Speed OFDM Receivers With Time-interleaved ADCS

With the rapid development of communications, most receiver functionalities areimplemented in digital signal processing (DSP) after analog to digital conversion. Torealize multi-Gigabit communication systems requires analog-to-digital conversions(ADCs) with high sampling rate and output resolution.A promising approach to realize such ADCs at reasonable power consumption is toemploy a time-interleaved (TI) architecture with slower (but power-efficient) sub-ADCsin parallel. However, mismatch among the sub-ADCs, if left uncompensated, can causeerror floors in receiver performance. In this thesis, we investigate the mismatchcorrection from two aspects, which are that mismatch correction is in ADCs module(module level) and mismatch correction is in equalizer (system level).We first characterize the structure of mismatch-indued interference for an OFDMsystem, and demostate the complexity of interference suppression will be reduced whenthe number of sub-ADC divides the number of sub-carrier.Then, we investigate correction algorithms for TIADC in module level. Theestimation of the proposed algorithm is based on the correlation between adjacentsub-ADCs and the calibration is based on perfect reconstruction. Meanwhile weinvestigate the circuits design for the proposed mismatch suppression algorithm. Weverify the availability of the correction circuits by using Altera Stratix III FPGA.Finally, we investigate correction algorithm for TIADC in system level, wheremismatch and channel dispersion are compensated jointly, with the performance metricbeing overall link reliability rather than ADC performance. And simulations show thatthe proposed jointly mismatch and channel compensation technique is close to thatwithout mismatch.